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📄 ds26528.h

📁 Sample driver code for Dallas DS26528 T1/E1 framer chip.
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/* 
 * Copyright 1997-2005 NComm, Inc.  All rights reserved.
 * 
 *
 *                     *** Important Notice ***
 * The software contained in this file may only be used within a 
 * valid license agreement between your company and NComm, Inc. 
 * The license agreement includes the definition of a PROJECT which 
 * defines the scope that this software can be used in.  Any use outside of
 * the definition of the PROJECT is prohibited without executing an additional 
 * agreement with NComm, Inc. Please refer to you license agreement for 
 * the definition of the PROJECT.
 *
 * Verification of your company's license agreement and copies of 
 * that agreement also may be obtained from:
 *
 * NComm, Inc.
 * 254 N Broadway
 * Suite 106
 * Salem, NH 03079
 * (603) 893-6186
 * sales@ncomm.com
 *
 */


#ifndef DS26528_H
#define DS26528_H

typedef volatile unsigned char VUC;
typedef unsigned char UC;

#define VUC_FIELD(a, b, c) (((a) & (0xff >> (8 - (c)))) << (b))



typedef struct {

struct _te1span {
/*************************************************************************
 * Per Port Section
 *************************************************************************
*/

/*************************************************************************
 * Framer Receive Side
 *************************************************************************
*/
	VUC hole[16]; 	/* 0 - 00F */

	VUC rhc;	/* 010 */
#define RHC_RCRCD	(1 << 7)
#define RHC_RHR		(1 << 6)
#define RHC_RHMS	(1 << 5)
#define RHC_RHCS(x)	VUC_FIELD(x, 0, 5)

	VUC rhbse;	/* 011 */
#define RHBSE_RCM(x)	VUC_FIELD(x, 0, 5)

	VUC rdsosel;	/* 012 */
#define RDS0SEL_RCM(x)	VUC_FIELD(x, 0, 5)

	VUC rsigc;	/* 013 */
#define RSIGC_RFSA1	(1 << 4)
#define RSIGC_RSFF	(1 << 2)
#define RSIGC_RSFE	(1 << 1)
#define RSIGC_RSIE	(1 << 0)

#define RSIGC_CASMS	(1 << 4)

	VUC rcr2;	/* 014 */
#define RCR2_RSLC96	(1 << 4)
#define RCR2_OOF(x)	VUC_FIELD(x, 2, 2)
#define RCR2_RAIIE 	(1 << 1)
#define RCR2_RD4RM	(1 << 0)

#define RCR2_RSA4IM	(1 << 4)
#define RCR2_RSA5IM	(1 << 3)
#define RCR2_RSA6IM	(1 << 2)
#define RCR2_RSA7IM	(1 << 1)
#define RCR2_RSA8IM	(1 << 0)

	VUC rbocc;	/* 015 */
#define RBOCC_RBR	(1 << 7)
#define RBOCC_RBD(x)	VUC_FIELD(x, 4, 2)
#define RBOCC_RBF(x)	VUC_FIELD(x, 1, 2)

	VUC hole2[10];	/* 016 - 01F */

	VUC ridr[32];	/* 020 - 040 */

	VUC rs[16];	/* 040 - 04F */

	VUC lcvcr1;	/* 050 */
#define LCVCR1_LCVC(x)	VUC_FIELD(x, 1, 7)
#define LCVCR1_LCCV8	(1 << 0)

	VUC lcvcr2;	/* 051 */
#define LCVCR2_(x)	VUC_FIELD(x, 0, 8)

	VUC pcvcr1;	/* 052 */
#define PCVCR1_PCVC(x)	VUC_FIELD(x, 0, 8)

	VUC pcvcr2;	/* 053 */
#define PCVCR2_PCVC(x)	VUC_FIELD(x, 0, 8)

	VUC foscr1;	/* 054 */
#define FOSCR1_FOS(x)	VUC_FIELD(x, 0, 8)

	VUC foscr2;	/* 055 */
#define FOSCR2_FOS(x)	VUC_FIELD(x, 0, 8)

	VUC ebcr1;	/* 056 */
	
	VUC ebcr2;	/* 057 */

	VUC hole6[8];	/* 058 - 05F */

	VUC rdsom; 	/* 060 */
#define RDSOM_B(x)	VUC_FIELD(x, 0, 8)

	VUC hole7; 	/* 061 */

	VUC rfdl_rrts7;	/* 062 */
#define RFDL_RFDL(x)	VUC_FIELD(x, 0, 8)

#define RRTS7_CSC5(x)	VUC_FIELD(x, 3, 5)
#define RRTS7_CRC4SA	(1 << 2)
#define RRTS7_CASSA	(1 << 1)
#define RRTS7_CFASSA	(1 << 0)

	VUC rboc;	/* 063 */
#define RBOC_RBOC(x)	VUC_FIELD(x, 0, 6)

	VUC rslc1_raf; 	/* 064 */
#define RAF_SI		(1 << 7)

	VUC rslc2_rnaf;  	/* 065 */
#define RNAF_SI		(1 << 7)
#define RNAF_A		(1 << 5)
#define RNAF_SA4	(1 << 4)
#define RNAF_SA5	(1 << 3)
#define RNAF_SA6	(1 << 2)
#define RNAF_SA7	(1 << 1)
#define RNAF_SA8	(1 << 0)

	VUC rslc3_rsiaf; /* 066 */
	
	VUC rsinaf;	/* 067 */

	VUC rra;	/* 068 */
	
	VUC rsa4;	/* 069 */

	VUC rsa5;	/* 06A */

	VUC rsa6;	/* 06B */

	VUC rsa7;	/* 06C */

	VUC rsa8;	/* 06D */

	VUC sabits;	/* 06E */

	VUC sa6code;	/* 06F */

	VUC hole8[16]; 	/* 070 - 07F */

	VUC rmmr; 	/* 080 */
#define RMMR_FRM_EN	(1 << 7)
#define RMMR_INIT_DONE	(1 << 6)
#define RMMR_SFTRST	(1 << 1)
#define RMMR_T1E1	(1 << 0)

	VUC rcr1; /* 081 */
#define RCR1_SYNCT	(1 << 7)
#define RCR1_RB8ZS	(1 << 6)
#define RCR1_RFM	(1 << 5)
#define RCR1_ARC	(1 << 4)
#define RCR1_SYNCC	(1 << 3)
#define RCR1_RJC	(1 << 2)
#define RCR1_SYNCE	(1 << 1)
#define RCR1_RESYNC	(1 << 0)

#define RCR1_RHDB3	(1 << 6)
#define RCR1_RSIGM	(1 << 5)
#define RCR1_RG802	(1 << 4)
#define RCR1_RCRC4	(1 << 3)
#define RCR1_FRC	(1 << 2)

	VUC ribcc_rcr2; /* 082 */
#define RIBCC_RUP(x)	VUC_FIELD(x, 3, 3)
#define RIBCC_RDN(x)	VUC_FIELD(x, 0, 3)

#define RCR2_RSAS(x)	VUC_FIELD(x, 3, 5)
#define RCR2_RLOSA	(1 << 0)

	VUC rcr3; /* 083 */
#define RCR3_IDF	(1 << 7)
#define RCR3_RSERC	(1 << 5)
#define RCR3_RLB	(1 << 2)
#define RCR3_PLB	(1 << 1)
#define RCR3_FLB	(1 << 0)

	VUC riocr;	/* 084 */
#define RIOCR_RCLKINV	(1 << 7)
#define RIOCR_RSYNCINV	(1 << 6)
#define RIOCR_H100EN	(1 << 5)
#define RIOCR_RSCLKM	(1 << 4)
#define RIOCR_RSMS	(1 << 3)
#define RIOCR_RSIO	(1 << 2)
#define RIOCR_RSMS2	(1 << 1)
#define RIOCR_RSMS1	(1 << 0)

	VUC rescr;	/* 085 */
#define RESCR_RDATFMT	(1 << 7)
#define RESCR_RGCLKEN	(1 << 6)
#define RESCR_RSZS	(1 << 4)
#define RESCR_RESALGN	(1 << 3)
#define RESCR_RESR	(1 << 2)
#define RESCR_RESMDM	(1 << 1)
#define RESCR_RESE	(1 << 0)

	VUC ercnt;	/* 086 */
#define ERCNT_1SECS	(1 << 7)
#define ERCNT_MCUS	(1 << 6)
#define ERCNT_MECU	(1 << 5)
#define ERCNT_ECUS	(1 << 4)
#define ERCNT_EAMS	(1 << 3)
#define ERCNT_FSBE	(1 << 2)
#define ERCNT_MOSCRF	(1 << 1)
#define ERCNT_LCVCRF	(1 << 0)

	VUC rhfc;	/* 087 */
#define RHFC_RFHWM(x)	VUC_FIELD(x, 0, 2)

	VUC riboc;	/* 088 */
#define RIBOC_IBS(x)	VUC_FIELD(x, 5, 2)
#define RIBOC_IBOSEL	(1 << 4)
#define RIBOC_IBOEN	(1 << 3)
#define RIBOC_DA(x)	VUC_FIELD(x, 0, 3)

	VUC rscc;	/* 089 */
#define RSCC_RSC(x)	VUC_FIELD(x, 0, 3)

	VUC rxpc;	/* 08A */

	VUC rbpbs;	/* 08B */
#define RBPBS_BPBSE(x)	VUC_FIELD(x, 0, 8)

	VUC hole9[2];	/* 08C - 08D */

	VUC rtest5;	/* 08E */
#define RTEST5_RTD(x)	VUC_FIELD(x, 0, 8)

	VUC rtest6;	/* 08F */
#define RTEST6_RHRTE	(1 << 7)
#define RTEST6_RLRTE	(1 << 6)
#define RTEST6_ISTML	(1 << 3)
#define RTEST6_ISTLL	(1 << 2)
#define RTEST6_FTML	(1 << 1)
#define RTEST6_FTLL	(1 << 0)

	VUC rls1;	/* 090 */
#define RLS1_RRAIC	(1 << 7)
#define RLS1_RAISC	(1 << 6)
#define RLS1_RLOSC	(1 << 5)
#define RLS1_RLOFC	(1 << 4)
#define RLS1_RRAID	(1 << 3)
#define RLS1_RAISD	(1 << 2)
#define RLS1_RLOSD	(1 << 1)
#define RLS1_RLOFD	(1 << 0)

	VUC rls2;	/* 091 */
#define RLS2_RPDV	(1 << 7)
#define RLS2_COFA 	(1 << 5)
#define RLS2_8ZD 	(1 << 4)
#define RLS2_16ZD	(1 << 3)
#define RLS2_SEFE	(1 << 2)
#define RLS2_B8ZS	(1 << 1)
#define RLS2_FBE	(1 << 0)

#define RLS2_CRCRC	(1 << 6)
#define RLS2_CASRC	(1 << 5)
#define RLS2_FASRC	(1 << 4)
#define RLS2_RSA(x)	VUC_FIELD(x, 2, 2)
#define RLS2_RCMF	(1 << 1)
#define RLS2_RAF	(1 << 0)

	VUC rls3;	/* 092 */
#define RLS3_LORCC 	(1 << 7)
#define RLS3_LSPC	(1 << 6)
#define RLS3_LDNC 	(1 << 5)
#define RLS3_LUPC	(1 << 4)
#define RLS3_LORCD	(1 << 3)
#define RLS3_LSPD	(1 << 2)
#define RLS3_LDND	(1 << 1)
#define RLS3_LUPD	(1 << 0)

	VUC rls4;	/* 093 */
#define RLS4_RESF	(1 << 7)
#define RLS4_RESEM	(1 << 6)
#define RLS4_RSLIP	(1 << 5)
#define RLS4_RSCOS	(1 << 3)
#define RLS4_1SEC	(1 << 2)
#define RLS4_TIMER	(1 << 1)
#define RLS4_RMF	(1 << 0)

	VUC rls5;	/* 094 */
#define RLS5_ROVR	(1 << 5)
#define RLS5_RHOBT	(1 << 4)
#define RLS5_RPE	(1 << 3)
#define RLS5_RPS	(1 << 2)
#define RLS5_RHWMS	(1 << 1)
#define RLS5_RNES	(1 << 0)

	VUC hole10;	/* 095 */

	VUC rls7;	/* 096 */
#define RLS7_RRAICI	(1 << 5)
#define RLS7_RAISCI	(1 << 4)
#define RLS7_RSLC96	(1 << 3)
#define RLS7_RFDLF	(1 << 2)
#define RLS7_BC		(1 << 1)
#define RLS7_BD		(1 << 0)

	VUC hole11;	/* 097 */

	VUC rss[3];	/* 098 - 09A */

	VUC hole12;	/* 09B */

	VUC rspcd1;	/* 09C */
#define RSPCD1_C(x)	VUC_FIELD(x, 0, 8)

	VUC rspcd2;	/* 09D */
#define RSPCD2_C(x)	VUC_FIELD(x, 0, 8)

	VUC hole13;	/* 09E */

	VUC riir;	/* 09F */
#define RIIR_RLS(x)	VUC_FIELD(x, 0, 7)

	VUC rim1;	/* 0A0 */
#define RIM1_RRAIC	(1 << 7)
#define RIM1_RAISC	(1 << 6)
#define RIM1_RLOSC	(1 << 5)
#define RIM1_RLOFC	(1 << 4)
#define RIM1_RRAID	(1 << 3)
#define RIM1_RAISD	(1 << 2)
#define RIM1_RLOSD	(1 << 1)
#define RIM1_RLOFD	(1 << 0)

	VUC rim2;	/* 0A1 */
#define RIM2_RSA1	(1 << 3)
#define RIM2_RSA0	(1 << 2)
#define RIM2_RCMF	(1 << 1)
#define RIM2_RAF	(1 << 0)

	VUC rim3;	/* 0A2 */
#define RIM3_LORCC	(1 << 7)
#define RIM3_LSPC	(1 << 6)
#define RIM3_LDNC	(1 << 5)
#define RIM3_LUPC	(1 << 4)
#define RIM3_LORCD	(1 << 3)
#define RIM3_LSPD	(1 << 2)
#define RIM3_LDND	(1 << 1)
#define RIM3_LUPD	(1 << 0)

	VUC rim4;	/* 0A3 */
#define RIM4_RESF	(1 << 7)
#define RIM4_RESEM	(1 << 6)
#define RIM4_RSLIP	(1 << 5)
#define RIM4_RSCOS	(1 << 4)
#define RIM4_1SEC	(1 << 2)
#define RIM4_TIMER	(1 << 1)
#define RIM4_RMF	(1 << 0)

	VUC rim5;	/* 0A4 */
#define RIM5_ROVR	(1 << 5)
#define RIM5_RHOBT	(1 << 4)
#define RIM5_RPE	(1 << 3)
#define RIM5_RPS	(1 << 2)
#define RIM5_RHWMS	(1 << 1)
#define RIM5_RNES	(1 << 0)

	VUC hole15;	/* 0A5 */

	VUC rim7;	/* 0A6 */
#define RIM7_RRAICI	(1 << 5)
#define RIM7_RAISCI	(1 << 4)
#define RIM7_RSLC96	(1 << 3)
#define RIM7_RFDLF	(1 << 2)
#define RIM7_BC		(1 << 1)
#define RIM7_BD		(1 << 0)
#define RIM7_SA6CD	(1 << 1)
#define RIM7_SAXCD	(1 << 0)

	VUC hole16;	/* 0A7 */

	VUC rscse[4];	/* 0A8 - 0AB */

	VUC rupcd1;	/* 0AC */
#define RUPCD_C(x)	VUC_FIELD(x, 0, 8)

	VUC rupcd2;	/* OAD */
#define RUPCD2_C(x)	VUC_FIELD(x, 0, 8)

	VUC rdncd1;	/* 0AE */
#define RDNCD1_C(x)	VUC_FIELD(x, 0, 8)

	VUC rdncd2;	/* 0AF */
#define RDNCD2_C(x)	VUC_FIELD(x, 0, 8)

	VUC rrts1;	/* 0B0 */
#define RRTS1_RRAI	(1 << 3)
#define RRTS1_RAIS	(1 << 2)
#define RRTS1_RLOS	(1 << 1)
#define RRTS1_RLOF	(1 << 0)

	VUC hole18;	/* 0B1 */

	VUC rrts3;	/* 0B2 */
#define RRTS3_LORC	(1 << 3)
#define RRTS3_LSP	(1 << 2)
#define RRTS3_LDN	(1 << 1)
#define RRTS3_LUP	(1 << 0)

#define RRTS3_V52LNK	(1 << 1)
#define RRTS3_RDMA	(1 << 0)

	VUC hole19;	/* 0B3 */

	VUC rrts5;	/* 0B4 */
#define RRTS5_PS(x)	VUC_FIELD(x, 4, 3)
#define RRTS5_RHWM	(1 << 1)
#define RRTS5_RNE	(1 << 0)

	VUC rhpba;	/* 0B5 */
#define RHPBA_MS 	(1 << 7)
#define RHPBA_RPBA(x)	VUC_FIELD(x, 7, 0)

	VUC rhf;	/* 0B6 */
#define RHF_RHD(x)	VUC_FIELD(x, 0, 8)

	VUC hole20[9];	/* 0B7 - 0B5 */

	VUC rbcs[4];	/* 0C0 - 0C3 */

	VUC rcbr[4];	/* 0C4 - 0C7 */

	VUC rsi[4];	/* 0C8 - 0CB */

	VUC rgccs[4];	/* OCC - 0CF */

	VUC rcice[4];	/* ODO - 0D3 */

	VUC rbpcs[4];	/* 0D4 - 0D7 */

	VUC hole22[24];	/* 0D8 - 0EF */

	
/*************************************************************************
 * End Framer Receive Side
 *************************************************************************
*/

/*************************************************************************
 * Global Register Map Section
 *************************************************************************
*/
	VUC gtcr1; 	/* 00f0 */
#define GTCR1_RLOFLTS	(1 << 5)
#define GTCR1_GIBO	(1 << 4)
#define GTCR1_BWE	(1 << 2)
#define GTCR1_GCLE	(1 << 1)
#define GTCR1_GIPI	(1 << 0)

	VUC gfcr;	/* 00f1 */
#define GFCR_IBOMS(x)	VUC_FIELD(x, 6, 2)
#define GFCR_BPCLK(x)	VUC_FIELD(x, 4, 2)
#define GFCR_RLOSSFS	(1 << 3)
#define GFCR_RFMSS	(1 << 2)
#define GFCR_TCBCS	(1 << 1)
#define GFCR_RCBCS	(1 << 0)

	VUC gtcr2;	/* 00f2 */
#define GTCR2_LOSS	(1 << 2)
#define GTCR2_TSSYNIOSEL (1 << 1)

	VUC gtccr;	/* 00f3 */
#define GTCCR_BPREFSEL(x) VUC_FIELD(x, 4, 4)
#define GTCCR_BPFREQSEL	(1 << 3)
#define GTCCR_FREQSEL	(1 << 2)
#define GTCCR_MPS(x)	VUC_FIELD(x, 0, 2)

	VUC hole101;	/* 00f4 */

	VUC glsrr;	/* 00f5 */

	VUC gfsrr;	/* 00f6 */

	VUC hole102;	/* 00f7 */
	
	VUC dimd;	/* 00f8 */

	VUC gfisr;	/* 00f9 */

	VUC gbisr;	/* 00fa */

	VUC glisr;	/* 00fb */

	VUC gfimr;	/* 00fc */

	VUC gbimr;	/* 00fd */

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