ds26528t1.c

Sample driver code for Dallas DS26528 T1/E1 framer chip.

	if(set_clear) {
		retval = hook_isr(sptr, set_clear, INTFLAG_LOOP);
		if(!retval)
			return(0);
		f->rim3 |= RIM3_LDND | RIM3_LUPD | RIM3_LDNC | RIM3_LUPC;
	}
	else {
		retval = hook_isr(sptr, set_clear, INTFLAG_LOOP);
		if(!retval)
			return(0);
		f->rim3 &= ~(RIM3_LDND | RIM3_LUPD | RIM3_LDNC | RIM3_LUPC);
	}

	return(retval);
}

/*------------------------------------------------------------------------*/
/* This routine sets up the clock used for the transmitter 
 */
static int set_txclock(STUFF *sptr, CLOCK_TYPE txclk)
{
int retval = 1;
STANDARD_DECLARE;

	switch(txclk) {
	case SYSCLOCK:	/* clock from central timing source */
		/* The TCLK pin */
		f->tcr3 = (f->tcr3 & (~TCR3_TCSS(3))) | TCR3_TCSS(0);
		break;

	case RXCLOCK:	/* loop timing selection */
		f->tcr3 = (f->tcr3 & (~TCR3_TCSS(3))) | TCR3_TCSS(3);
		break;

	case LOCALOSC:	/* clock from a local oscillator */
	case OTHERCLK:	/* some other clock selection */
	default:
		retval = 0;
		break;
	}
	
	return(retval);
}

/*------------------------------------------------------------------------*/
/* Enable T1.403 processing
 */
static int t1403_init(STUFF *sptr, int set_clear)
{
int retval = 1 , i;
STANDARD_DECLARE;

	if(set_clear) {
		retval = hook_isr(sptr, set_clear, INTFLAG_T1403);
		if(!retval)
			return(0);
		

		/* Reset the HDLC channels */
		f->rhc |= RHC_RHR;
		f->rhc &= ~RHC_RHR;
		f->thc1 |= THC1_THR;
		f->thc1 &= ~THC1_THR;

		f->rbocc |= RBOCC_RBR;
		/* wait for the reset bit to clear */
		for(i = 0; i < MAX_RESET_WAIT; i++)
			if(!(f->rbocc & RBOCC_RBR)) break;

		if( i >= MAX_RESET_WAIT) {
			/* Reset should have finished by now, 
			 * this is an error */
			(*sptr->cback)(sptr->lnPtr, TE1DCLBK_FATALERROR, 0);
		}
		
		f->rbocc = RBOCC_RBD(1) | RBOCC_RBF(1);
		f->txpc = TXPC_THPAMS | TXPC_THPAEN;
		f->rhfc = RHFC_RFHWM(HIGH_WATER_MARK);
		f->thfc = THFC_TFLWM(LOW_WATER_MARK);
		f->rim5 |= RIM5_RPS;	
		f->thc1 = THC1_THMS;
		f->thc2 |= THC2_THCEN;

	}
	else {

		f->rhc |= RHC_RHR;
		f->thc1 |= THC1_THR;
		f->thc2 &= ~THC2_THCEN;

		retval = hook_isr(sptr, set_clear, INTFLAG_T1403);
		if(!retval)
			return(0);
	}

	return(retval);
}

/*------------------------------------------------------------------------*/
/* processes sending hdlc packets.
 * The packet has already been copied into the sptr area 
 * The flag = 1 means this is the start of the send
 * if flag = 0, means that this is a subsequent part of the packet
 * if flag = 2, means turn off the HDLC packet facility
 */
static int send_fdl_packet(STUFF *sptr, int flag)
{
int retval = 1;
STANDARD_DECLARE;

	switch(flag) {
	case 0:
		break;
	case 1:
		sptr->t1s.sendingBOC = 0;

		f->thc2 &= ~(THC2_SBOC);
		f->tcr2 |= TCR2_TFDLS;
		sptr->t1s.txremaining = sptr->pkttx.byte_count;
		sptr->t1s.sendingPKT = 1;
		hdlc_xmit(sptr);

		break;
	case 2:
		f->tim2 = 0;
		f->rim7 &= ~(RIM7_BC | RIM7_BD);
		f->thc2 &= ~(THC2_SBOC);
		f->rhc = 0;

		f->thc1 = 0;
		f->tcr2 &= ~TCR2_TFDLS;
		f->rhc = RHC_RHR | RHC_RHMS;

		f->thc1 = THC1_THR | THC1_THMS;
		break;
	default:
		retval = 0;
		break;
	}
	return(retval);
}

/*------------------------------------------------------------------------*/
/* processes sending BOC codes
 * the boc code and the action has already been coped into the
 * sptr area
 */
static int send_fdl_boc(STUFF *sptr)
{
int retval = 1;
STANDARD_DECLARE;

	if(sptr->boctx.active) {
		if(sptr->t1s.sendingPKT) {
		   unsigned long imask;

			imask = INTS_OFF();

			f->tim2 &= 
			  ~(TIM2_TLWMS | TIM2_TNFS | TIM2_TMEND);

			f->thc1 = THC1_THR | THC1_THMS;
			f->thc1 = THC1_THMS;

			INTS_ON(imask);
		}
			
		sptr->t1s.sendingPKT = 0;
		sptr->t1s.txremaining = 0;
		sptr->t1s.sendingBOC = 1;

		/* send the BOC
		 */

		f->tcr2 &= ~TCR2_TFDLS;
		f->tboc = (sptr->boctx.boc >> 1);
		f->thc2 |= THC2_SBOC;

	}
	else {
		sptr->t1s.sendingBOC = 0;
		f->thc2 &= ~(THC2_SBOC);
	}
	return(retval);
}

/*------------------------------------------------------------------------*/
/* Enable TR-54016 processing
 */
static int tr54016_init(STUFF *sptr, int set_clear)
{
int retval = 1;

	/* Nothing to do on DS26528 */

	return(retval);
}

/*------------------------------------------------------------------------*/
/* Enable TR-00008 processing
 * This prepares the device to start tx and receive of TR-0008 items.
 */
static int tr008_init(STUFF *sptr, int set_clear)
{
int retval = 1;

	if(set_clear) {
		/* !!! Enable TR-00008 processing here !!! */
	}
	else {
		/* !!! Diable TR-00008 processing here !!! */
	}

	return(retval);
}

/*------------------------------------------------------------------------*/
/* Enable EXZ processing
 * This enables counting BPVs and EXZ at the same time
 * When disabled, EXZ are not counted.  Used for the BPV alarm
 * during TR-00008 applications, and enabled other times.
 */
static int exz_init(STUFF *sptr, int set_clear)
{
int retval = 1;
STANDARD_DECLARE;


	if(set_clear) {
		f->ercnt |= ERCNT_LCVCRF;
	}
	else {
		f->ercnt &= ~(ERCNT_LCVCRF);
	}

	return(retval);
}

/*------------------------------------------------------------------------*/
/* Enable the CMAS bit processing for TR-00008 applications
 * CMAS_C = 0x01 =concentration field
 * CMAS_M = 0x02 =Maintenance field
 * CMAS_A = 0x04 =Alarm field
 * CMAS_S = 0x08 =Protection Switching field
 */
static int cmas_init(STUFF *sptr, int cmas)
{
int retval = 1;

	if(cmas & 0x01) {
		/* !!! Enable the concentration bits here !!! */
	}
	else {
		/* !!! Disable the concentration bits here !!! */
	}

	if(cmas & 0x02) {
		/* !!! Enable the maintenance bits here !!! */
	}
	else {
		/* !!! Disable the maintenance bits here !!! */
	}

	if(cmas & 0x04) {
		/* !!! Enable the Alarm bits here !!! */
	}
	else {
		/* !!! Disable the Alarm bits here !!! */
	}

	if(cmas & 0x08) {
		/* !!! Enable the Protection Switching bits here !!! */
	}
	else {
		/* !!! Disable the Protection Switching bits here !!! */
	}

	return(retval);
}

/*------------------------------------------------------------------------*/
/* 
 * This routine sets up the configration of the channel
 * sptr is the pointer to the stuff structure
 */
static int _t1Config(STUFF *sptr)
{
int retval = 1;
unsigned char value2 = 0;
LIU *l = sptr->t1s.myliu;
STANDARD_DECLARE;


	switch(sptr->cfg.framing) {
	case FF_D4:
		f->tcr3 |= TCR3_TFM;
		f->rcr1 |= RCR1_RFM;
		f->tcr2 &= ~TCR2_TFDLS;
		f->tfdl = 0x1c;
		break;

	case FF_ESF:
		f->tcr3 &= ~TCR3_TFM;
		f->rcr1 &= ~RCR1_RFM;
		f->tcr2 |= TCR2_TFDLS;
		f->tfdl = 0x7e;
		break;

	case FF_SLC96:
		f->tcr2 |= TCR2_TSLC96;
		break;

	default:
		return(0);
	}

	switch(sptr->cfg.coding) {
	case LC_B8ZS:
		f->tcr1 |= TCR1_TB8ZS;
		f->rcr1 |= RCR1_RB8ZS;
		f->tcr2 &= ~TCR2_PDE;
		break;

	case LC_AMI:
		f->tcr1 &= ~TCR1_TB8ZS;
		f->rcr1 &= ~RCR1_RB8ZS;
		f->tcr2 |= TCR2_PDE;
		break;

	default:
		return(0);
	}

	/* Handle Line Build Out */


	if(sptr->cfg.lbo == -1) {	/* 0 db LH */
		value2 = 0;
	}
	else if(sptr->cfg.lbo == -2) {	/* -7.5 db LH */
		value2 = 5;
	}
	else if(sptr->cfg.lbo == -3) {	/* -15 db LH */
		value2 = 6;
	}
	else if(sptr->cfg.lbo == -4) {	/* -22.5 db LH */
		value2 = 7;
	}
	else if(sptr->cfg.lbo <= 133) {
		value2 = 0;
	}
	else if(sptr->cfg.lbo <= 266) {
		value2 = 1;
	}
	else if(sptr->cfg.lbo <= 399) {
		value2 = 2;
	}
	else if(sptr->cfg.lbo <= 533) {
		value2 = 3;
	}
	else if(sptr->cfg.lbo <= 655) {
		value2 = 4;
	}

	l->ltitsr = (l->ltitsr & 0xf1) | value2;

	if(sptr->cfg.lbo < 0) {
		/* long haul */
		l->lrismr = (l->lrismr & 0x03) | LRISMR_RSMS(1);
	} else {
		/* short haul */
		l->lrismr = (l->lrismr & 0x03) | LRISMR_RSMS(3);
	}

	return(retval);
}

/*------------------------------------------------------------------------*/
/* 
 * This routine resets the T1 portion of the chip.
 * sptr is the pointer to the stuff structure
 */
static int _te1Reset(STUFF *sptr)
{
int retval = 1;
LIU *l = sptr->t1s.myliu;
STANDARD_DECLARE;

	if(!sptr->greset){
		NCID_GRESET(sptr->d);
		sptr->greset = 1;
	}

	utility_init(sptr, (sptr->utility_init = 0));
	alarm_init(sptr, (sptr->alarm_init = 0));
	onesec_init(sptr, (sptr->onesec_init = 0));
	t1403_init(sptr, (sptr->t1403_init = 0));
	loop_init(sptr, (sptr->loop_init = 0));

	/* Soft Reset into T1 mode */

	f->tmmr = TMMR_SFTRST;
	f->tmmr = 0;
	
	f->rmmr = RMMR_SFTRST;
	f->rmmr = 0;

	f->tmmr = TMMR_FRM_EN;
	f->rmmr = RMMR_FRM_EN;
	
	f->rcr1 = RCR1_SYNCC |
		((RESYNC_CRITERIA | RX_UNIPOLAR) ? RCR1_ARC : 0) |
		((SYNC_TIME) ? RCR1_SYNCT : 0);

	f->rcr3 = (RX_UNIPOLAR) ? RCR3_IDF : 0;

	f->riocr = ((RSYNC_MODE1) ? RIOCR_RSMS1 : 0) |
		((RSYNC_MODE2_T1) ? RIOCR_RSMS2 : 0) |
		((RSYNC_IO_SELECT) ? RIOCR_RSIO : 0) |
		((RSYNC_SKIP) ? RIOCR_RSMS : 0) |
		((RSYNC_CLK_MODE_T1) ? RIOCR_RSCLKM : 0) |
		((H100_MODE) ? RIOCR_H100EN : 0) |
		((RSYNC_INV) ? RIOCR_RSYNCINV : 0) |
		((RCLK_INV) ? RIOCR_RCLKINV : 0);

	f->rescr = ((RX_ELASTIC_STORE_EN) ? RESCR_RESE : 0) |
		((RES_MIN_DELAY) ? RESCR_RESMDM : 0) |
		((RXS_ZONE_SEL) ? RESCR_RSZS : 0) |
		((GAP_CLOCK_EN) ? RESCR_RGCLKEN : 0) |
		((RX_CHAN_FORMAT) ? RESCR_RDATFMT : 0);

	f->ercnt =
		((MOS_COUNT_SELECT) ? ERCNT_MOSCRF : 0) |
		((PCVCR_SELECT) ? ERCNT_FSBE : 0) |
		((ERROR_ACU_MODE) ? ERCNT_EAMS : 0) |
		((UPDATE_SELECT_T1) ? ERCNT_ECUS : 0) |
		((MANUAL_UPDATE_SEL) ? ERCNT_MCUS : 0) |
		((ONE_SECOND_SEL) ? ERCNT_1SECS : 0);

	f->riboc = (RIBOC_DA(DEVICE_ASSIGNMENT)) |
		((IBO_EN) ? RIBOC_IBOEN : 0) |
		((IBO_SEL) ? RIBOC_IBOSEL : 0) |
		(RIBOC_IBS(IBO_SIZE));
	
	f->tiboc = (TIBOC_DA(DEVICE_ASSIGNMENT)) |
		((IBO_EN) ? TIBOC_IBOEN : 0) |
		((IBO_SEL) ? TIBOC_IBOSEL : 0) |
		(TIBOC_IBS(IBO_SIZE));
	
	f->tcr3 = (TX_UNIPOLAR) ? TCR3_ODF : 0;

	f->tiocr = ((TSYNC_MODE) ? TIOCR_TSM : 0) |
		((TSYNC_DOUBLE_WIDE) ? TIOCR_TSDW : 0) |
		((TSYNC_IO) ? TIOCR_TSIO : 0) |
		((TSSYNC_MODE) ? TIOCR_TSSM : 0) |
		((TSYSCLK_MODE_T1) ? TIOCR_TSCLKM : 0) |
		((TSYNCIO_INV) ? TIOCR_TSSYNCINV : 0) |
		((TSYNC_INV) ? TIOCR_TSYNCINV : 0) |
		((TCLK_INV) ? TIOCR_TCLKINV : 0);

	f->tescr = ((TX_ELASTIC_STORE_EN) ? TESCR_TESE : 0) |
		((TES_MIN_DELAY) ? TESCR_TESMDM : 0) |
		((TXS_ZONE_SEL) ? TESCR_TSZS : 0) |
		((TDATA_EN) ? TESCR_TDATAEN : 0) |
		((TGAP_CLOCK_EN) ? TESCR_TGCLKEN : 0) |
		((TX_CHAN_FORMAT) ? TESCR_TDATFMT : 0);


	l->ltrcr = ((JAT_DEPTH) ? LTRCR_JADS : 0) |
		(LTRCR_JAPS(JAT_POSITION)) |
		LTRCR_T1J1E1 |
		((LOS_CRITERIA) ? LTRCR_LSC : 0);

	l->ltitsr = ((TXTERM_OFF) ? LTITSR_TIMPTOFF : 0) |
			(LTITSR_TIMPL(1));
	
	l->lrismr = ((RXTERM_OFF) ? LRISMR_RIMPOFF : 0) |
			(LRISMR_RSMS(1));


	retval = _t1Config(sptr);
	if(!retval)
		return(0);

	retval = transmit_alarm(sptr, TMS_TXAIS, 1);

	/* after the configuration turn on the framer */
	f->tmmr |= TMMR_INIT_DONE;
	f->rmmr |= RMMR_INIT_DONE;

	/* Turn on LIU output */
	l->lmcr = LMCR_TE;

	return(retval);
}


/*------------------------------------------------------------------------*/
/* 
 * This routine UN resets the T1 portion of the chip.
 * sptr is the pointer to the stuff structure
 */