📄 msp430xg46x.h
字号:
#define DMA0TSEL1 (0x0002) /* DMA channel 0 transfer select bit 1 */
#define DMA0TSEL2 (0x0004) /* DMA channel 0 transfer select bit 2 */
#define DMA0TSEL3 (0x0008) /* DMA channel 0 transfer select bit 3 */
#define DMA1TSEL0 (0x0010) /* DMA channel 1 transfer select bit 0 */
#define DMA1TSEL1 (0x0020) /* DMA channel 1 transfer select bit 1 */
#define DMA1TSEL2 (0x0040) /* DMA channel 1 transfer select bit 2 */
#define DMA1TSEL3 (0x0080) /* DMA channel 1 transfer select bit 3 */
#define DMA2TSEL0 (0x0100) /* DMA channel 2 transfer select bit 0 */
#define DMA2TSEL1 (0x0200) /* DMA channel 2 transfer select bit 1 */
#define DMA2TSEL2 (0x0400) /* DMA channel 2 transfer select bit 2 */
#define DMA2TSEL3 (0x0800) /* DMA channel 2 transfer select bit 3 */
#define DMA0TSEL_0 (0*0x0001u) /* DMA channel 0 transfer select 0: DMA_REQ (sw)*/
#define DMA0TSEL_1 (1*0x0001u) /* DMA channel 0 transfer select 1: Timer_A (TACCR2.IFG) */
#define DMA0TSEL_2 (2*0x0001u) /* DMA channel 0 transfer select 2: Timer_B (TBCCR2.IFG) */
#define DMA0TSEL_3 (3*0x0001u) /* DMA channel 0 transfer select 3: USCIA receive */
#define DMA0TSEL_4 (4*0x0001u) /* DMA channel 0 transfer select 4: USCIA transmit */
#define DMA0TSEL_5 (5*0x0001u) /* DMA channel 0 transfer select 5: DAC12_0CTL.DAC12IFG */
#define DMA0TSEL_6 (6*0x0001u) /* DMA channel 0 transfer select 6: ADC12 (ADC12IFG) */
#define DMA0TSEL_7 (7*0x0001u) /* DMA channel 0 transfer select 7: Timer_A (TACCR0.IFG) */
#define DMA0TSEL_8 (8*0x0001u) /* DMA channel 0 transfer select 8: Timer_B (TBCCR0.IFG) */
#define DMA0TSEL_9 (9*0x0001u) /* DMA channel 0 transfer select 9: UART1 receive */
#define DMA0TSEL_10 (10*0x0001u) /* DMA channel 0 transfer select 10: UART1 transmit */
#define DMA0TSEL_11 (11*0x0001u) /* DMA channel 0 transfer select 11: Multiplier ready */
#define DMA0TSEL_12 (12*0x0001u) /* DMA channel 0 transfer select 12: USCIB receive */
#define DMA0TSEL_13 (13*0x0001u) /* DMA channel 0 transfer select 13: USCIB transmit */
#define DMA0TSEL_14 (14*0x0001u) /* DMA channel 0 transfer select 14: previous DMA channel DMA2IFG */
#define DMA0TSEL_15 (15*0x0001u) /* DMA channel 0 transfer select 15: ext. Trigger (DMAE0) */
#define DMA1TSEL_0 (0*0x0010u) /* DMA channel 1 transfer select 0: DMA_REQ */
#define DMA1TSEL_1 (1*0x0010u) /* DMA channel 1 transfer select 1: Timer_A CCRIFG.2 */
#define DMA1TSEL_2 (2*0x0010u) /* DMA channel 1 transfer select 2: Timer_B CCRIFG.2 */
#define DMA1TSEL_3 (3*0x0010u) /* DMA channel 1 transfer select 3: USCIA receive */
#define DMA1TSEL_4 (4*0x0010u) /* DMA channel 1 transfer select 4: USCIA transmit */
#define DMA1TSEL_5 (5*0x0010u) /* DMA channel 1 transfer select 5: DAC12.0IFG */
#define DMA1TSEL_6 (6*0x0010u) /* DMA channel 1 transfer select 6: ADC12 (ADC12IFG) */
#define DMA1TSEL_7 (7*0x0010u) /* DMA channel 1 transfer select 7: Timer_A (TACCR0.IFG) */
#define DMA1TSEL_8 (8*0x0010u) /* DMA channel 1 transfer select 8: Timer_B (TBCCR0.IFG) */
#define DMA1TSEL_9 (9*0x0010u) /* DMA channel 1 transfer select 9: UART1 receive */
#define DMA1TSEL_10 (10*0x0010u) /* DMA channel 1 transfer select 10: UART1 transmit */
#define DMA1TSEL_11 (11*0x0010u) /* DMA channel 1 transfer select 11: Multiplier ready */
#define DMA1TSEL_12 (12*0x0010u) /* DMA channel 1 transfer select 12: USCIB receive */
#define DMA1TSEL_13 (13*0x0010u) /* DMA channel 1 transfer select 13: USCIB transmit */
#define DMA1TSEL_14 (14*0x0010u) /* DMA channel 1 transfer select 14: previous DMA channel DMA0IFG */
#define DMA1TSEL_15 (15*0x0010u) /* DMA channel 1 transfer select 15: ext. Trigger (DMAE0) */
#define DMA2TSEL_0 (0*0x0100u) /* DMA channel 2 transfer select 0: DMA_REQ */
#define DMA2TSEL_1 (1*0x0100u) /* DMA channel 2 transfer select 1: Timer_A CCRIFG.2 */
#define DMA2TSEL_2 (2*0x0100u) /* DMA channel 2 transfer select 2: Timer_B CCRIFG.2 */
#define DMA2TSEL_3 (3*0x0100u) /* DMA channel 2 transfer select 3: USCIA receive */
#define DMA2TSEL_4 (4*0x0100u) /* DMA channel 2 transfer select 4: USCIA transmit */
#define DMA2TSEL_5 (5*0x0100u) /* DMA channel 2 transfer select 5: DAC12.0IFG */
#define DMA2TSEL_6 (6*0x0100u) /* DMA channel 2 transfer select 6: ADC12 (ADC12IFG) */
#define DMA2TSEL_7 (7*0x0100u) /* DMA channel 2 transfer select 7: Timer_A (TACCR0.IFG) */
#define DMA2TSEL_8 (8*0x0100u) /* DMA channel 2 transfer select 8: Timer_B (TBCCR0.IFG) */
#define DMA2TSEL_9 (9*0x0100u) /* DMA channel 2 transfer select 9: UART1 receive */
#define DMA2TSEL_10 (10*0x0100u) /* DMA channel 2 transfer select 10: UART1 transmit */
#define DMA2TSEL_11 (11*0x0100u) /* DMA channel 2 transfer select 11: Multiplier ready */
#define DMA2TSEL_12 (12*0x0100u) /* DMA channel 2 transfer select 12: USCIB receive */
#define DMA2TSEL_13 (13*0x0100u) /* DMA channel 2 transfer select 13: USCIB transmit */
#define DMA2TSEL_14 (14*0x0100u) /* DMA channel 2 transfer select 14: previous DMA channel DMA1IFG */
#define DMA2TSEL_15 (15*0x0100u) /* DMA channel 2 transfer select 15: ext. Trigger (DMAE0) */
#define DMACTL1_ (0x0124) /* DMA Module Control 1 */
DEFW( DMACTL1 , DMACTL1_)
#define ENNMI (0x0001) /* Enable NMI interruption of DMA */
#define ROUNDROBIN (0x0002) /* Round-Robin DMA channel priorities */
#define DMAONFETCH (0x0004) /* DMA transfer on instruction fetch */
#define DMAIV_ (0x0126) /* DMA Interrupt Vector Word */
DEFW( DMAIV , DMAIV_)
#define DMA0CTL_ (0x01d0) /* DMA Channel 0 Control */
DEFW( DMA0CTL , DMA0CTL_)
#define DMA1CTL_ (0x01dc) /* DMA Channel 1 Control */
DEFW( DMA1CTL , DMA1CTL_)
#define DMA2CTL_ (0x01e8) /* DMA Channel 2 Control */
DEFW( DMA2CTL , DMA2CTL_)
#define DMAREQ (0x0001) /* Initiate DMA transfer with DMATSEL */
#define DMAABORT (0x0002) /* DMA transfer aborted by NMI */
#define DMAIE (0x0004) /* DMA interrupt enable */
#define DMAIFG (0x0008) /* DMA interrupt flag */
#define DMAEN (0x0010) /* DMA enable */
#define DMALEVEL (0x0020) /* DMA level sensitive trigger select */
#define DMASRCBYTE (0x0040) /* DMA source byte */
#define DMADSTBYTE (0x0080) /* DMA destination byte */
#define DMASRCINCR0 (0x0100) /* DMA source increment bit 0 */
#define DMASRCINCR1 (0x0200) /* DMA source increment bit 1 */
#define DMADSTINCR0 (0x0400) /* DMA destination increment bit 0 */
#define DMADSTINCR1 (0x0800) /* DMA destination increment bit 1 */
#define DMADT0 (0x1000) /* DMA transfer mode bit 0 */
#define DMADT1 (0x2000) /* DMA transfer mode bit 1 */
#define DMADT2 (0x4000) /* DMA transfer mode bit 2 */
#define DMASWDW (0*0x0040u) /* DMA transfer: source word to destination word */
#define DMASBDW (1*0x0040u) /* DMA transfer: source byte to destination word */
#define DMASWDB (2*0x0040u) /* DMA transfer: source word to destination byte */
#define DMASBDB (3*0x0040u) /* DMA transfer: source byte to destination byte */
#define DMASRCINCR_0 (0*0x0100u) /* DMA source increment 0: source address unchanged */
#define DMASRCINCR_1 (1*0x0100u) /* DMA source increment 1: source address unchanged */
#define DMASRCINCR_2 (2*0x0100u) /* DMA source increment 2: source address decremented */
#define DMASRCINCR_3 (3*0x0100u) /* DMA source increment 3: source address incremented */
#define DMADSTINCR_0 (0*0x0400u) /* DMA destination increment 0: destination address unchanged */
#define DMADSTINCR_1 (1*0x0400u) /* DMA destination increment 1: destination address unchanged */
#define DMADSTINCR_2 (2*0x0400u) /* DMA destination increment 2: destination address decremented */
#define DMADSTINCR_3 (3*0x0400u) /* DMA destination increment 3: destination address incremented */
#define DMADT_0 (0*0x1000u) /* DMA transfer mode 0: single */
#define DMADT_1 (1*0x1000u) /* DMA transfer mode 1: block */
#define DMADT_2 (2*0x1000u) /* DMA transfer mode 2: interleaved */
#define DMADT_3 (3*0x1000u) /* DMA transfer mode 3: interleaved */
#define DMADT_4 (4*0x1000u) /* DMA transfer mode 4: single, repeat */
#define DMADT_5 (5*0x1000u) /* DMA transfer mode 5: block, repeat */
#define DMADT_6 (6*0x1000u) /* DMA transfer mode 6: interleaved, repeat */
#define DMADT_7 (7*0x1000u) /* DMA transfer mode 7: interleaved, repeat */
#define DMA0SA_ (0x01d2) /* DMA Channel 0 Source Address */
#ifndef __IAR_SYSTEMS_ICC__
DEFA( DMA0SA , DMA0SA_)
#endif
#define DMA0SAL_ (0x01d2) /* DMA Channel 0 Source Address */
#ifndef __IAR_SYSTEMS_ICC__
DEFW( DMA0SAL , DMA0SAL_)
#endif
#ifdef __IAR_SYSTEMS_ICC__
__no_init union
{
DEFXW DMA0SAL;
DEFXA DMA0SA;
} @ 0x01D2;
#endif
#define DMA0DA_ (0x01d6) /* DMA Channel 0 Destination Address */
#ifndef __IAR_SYSTEMS_ICC__
DEFA( DMA0DA , DMA0DA_)
#endif
#define DMA0DAL_ (0x01d6) /* DMA Channel 0 Destination Address */
#ifndef __IAR_SYSTEMS_ICC__
DEFW( DMA0DAL , DMA0DAL_)
#endif
#ifdef __IAR_SYSTEMS_ICC__
__no_init union
{
DEFXW DMA0DAL;
DEFXA DMA0DA;
} @ 0x01D6;
#endif
#define DMA0SZ_ (0x01da) /* DMA Channel 0 Transfer Size */
DEFW( DMA0SZ , DMA0SZ_)
#define DMA1SA_ (0x01de) /* DMA Channel 1 Source Address */
#ifndef __IAR_SYSTEMS_ICC__
DEFA( DMA1SA , DMA1SA_)
#endif
#define DMA1SAL_ (0x01de) /* DMA Channel 1 Source Address */
#ifndef __IAR_SYSTEMS_ICC__
DEFW( DMA1SAL , DMA1SAL_)
#endif
#ifdef __IAR_SYSTEMS_ICC__
__no_init union
{
DEFXW DMA1SAL;
DEFXA DMA1SA;
} @ 0x01DE;
#endif
#define DMA1DA_ (0x01e2) /* DMA Channel 1 Destination Address */
#ifndef __IAR_SYSTEMS_ICC__
DEFA( DMA1DA , DMA1DA_)
#endif
#define DMA1DAL_ (0x01e2) /* DMA Channel 1 Destination Address */
#ifndef __IAR_SYSTEMS_ICC__
DEFW( DMA1DAL , DMA1DAL_)
#endif
#ifdef __IAR_SYSTEMS_ICC__
__no_init union
{
DEFXW DMA1DAL;
DEFXA DMA1DA;
} @ 0x01E2;
#endif
#define DMA1SZ_ (0x01e6) /* DMA Channel 1 Transfer Size */
DEFW( DMA1SZ , DMA1SZ_)
#define DMA2SA_ (0x01ea) /* DMA Channel 2 Source Address */
#ifndef __IAR_SYSTEMS_ICC__
DEFA( DMA2SA , DMA2SA_)
#endif
#define DMA2SAL_ (0x01ea) /* DMA Channel 2 Source Address */
#ifndef __IAR_SYSTEMS_ICC__
DEFW( DMA2SAL , DMA2SAL_)
#endif
#ifdef __IAR_SYSTEMS_ICC__
__no_init union
{
DEFXW DMA2SAL;
DEFXA DMA2SA;
} @ 0x01EA;
#endif
#define DMA2DA_ (0x01ee) /* DMA Channel 2 Destination Address */
#ifndef __IAR_SYSTEMS_ICC__
DEFA( DMA2DA , DMA2DA_)
#endif
#define DMA2DAL_ (0x01ee) /* DMA Channel 2 Destination Address */
#ifndef __IAR_SYSTEMS_ICC__
DEFW( DMA2DAL , DMA2DAL_)
#endif
#ifdef __IAR_SYSTEMS_ICC__
__no_init union
{
DEFXW DMA2DAL;
DEFXA DMA2DA;
} @ 0x01EE;
#endif
#define DMA2SZ_ (0x01f2) /* DMA Channel 2 Transfer Size */
DEFW( DMA2SZ , DMA2SZ_)
/* DMAIV Definitions */
#define DMAIV_NONE (0x0000) /* No Interrupt pending */
#define DMAIV_DMA0IFG (0x0002) /* DMA0IFG */
#define DMAIV_DMA1IFG (0x0004) /* DMA1IFG */
#define DMAIV_DMA2IFG (0x0006) /* DMA2IFG */
/*************************************************************
* Flash Memory
*************************************************************/
#define __MSP430_HAS_FLASH__ /* Definition to show that Module is available */
#define __MSP430_HAS_2FLASH_IP__ /* Definition to show that Module is available */
#define FCTL1_ (0x0128) /* FLASH Control 1 */
DEFW( FCTL1 , FCTL1_)
#define FCTL2_ (0x012A) /* FLASH Control 2 */
DEFW( FCTL2 , FCTL2_)
#define FCTL3_ (0x012C) /* FLASH Control 3 */
DEFW( FCTL3 , FCTL3_)
#define FRKEY (0x9600) /* Flash key returned by read */
#define FWKEY (0xA500) /* Flash key for write */
#define FXKEY (0x3300) /* for use with XOR instruction */
#define ERASE (0x0002) /* Enable bit for Flash segment erase */
#define MERAS (0x0004) /* Enable bit for Flash mass erase */
#define GMERAS (0x0008) /* Enable bit for Flash global mass erase */
#define CPUEX (0x0010) /* Enable bit for CPU Execution during Flash write/erase */
#define WRT (0x0040) /* Enable bit for Flash write */
#define BLKWRT (0x0080) /* Enable bit for Flash segment write */
#define SEGWRT (0x0080) /* old definition */ /* Enable bit for Flash segment write */
#define FN0 (0x0001) /* Divide Flash clock by 1 to 64 using FN0 to FN5 according to: */
#define FN1 (0x0002) /* 32*FN5 + 16*FN4 + 8*FN3 + 4*FN2 + 2*FN1 + FN0 + 1 */
#ifndef FN2
#define FN2 (0x0004)
#endif
#ifndef FN3
#define FN3 (0x0008)
#endif
#ifndef FN4
#define FN4 (0x0010)
#endif
#define FN5 (0x0020)
#define FSSEL0 (0x0040) /* Flash clock select 0 */ /* to distinguish from USART SSELx */
#define FSSEL1 (0x0080) /* Flash clock select 1 */
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -