📄 msp430xg46x.h
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DEFW( RTCTIM0 , RTCTIM0_)
#endif
#ifdef __IAR_SYSTEMS_ICC__
__no_init union
{
struct
{
DEFXC RTCNT1;
DEFXC RTCNT2;
};
DEFXW RTCTIM0;
} @ 0x0042;
#endif
#define RTCTIM1_ (0x0044) /* Real Time Clock Time 1 */
#ifndef __IAR_SYSTEMS_ICC__
DEFW( RTCTIM1 , RTCTIM1_)
#endif
#ifdef __IAR_SYSTEMS_ICC__
__no_init union
{
struct
{
DEFXC RTCNT3;
DEFXC RTCNT4;
};
DEFXW RTCTIM1;
} @ 0x0044;
#endif
#define BTCNT12_ (0x0046) /* Basic Timer Count 1/2 */
#ifndef __IAR_SYSTEMS_ICC__
DEFW( BTCNT12 , BTCNT12_)
#endif
#ifdef __IAR_SYSTEMS_ICC__
__no_init union
{
struct
{
DEFXC BTCNT1;
DEFXC BTCNT2;
};
DEFXW BTCNT12;
} @ 0x0046;
#endif
#define RTCDATE_ (0x004C) /* Real Time Clock Date */
#ifndef __IAR_SYSTEMS_ICC__
DEFW( RTCDATE , RTCDATE_)
#endif
#ifdef __IAR_SYSTEMS_ICC__
__no_init union
{
struct
{
DEFXC RTCDAY;
DEFXC RTCMON;
};
DEFXW RTCDATE;
} @ 0x004C;
#endif
#define RTCYEAR_ (0x004E) /* Real Time Clock Year */
#ifndef __IAR_SYSTEMS_ICC__
DEFW( RTCYEAR , RTCYEAR_)
#endif
#ifdef __IAR_SYSTEMS_ICC__
__no_init union
{
struct
{
DEFXC RTCYEARL;
DEFXC RTCYEARH;
};
DEFXW RTCYEAR;
} @ 0x004E;
#endif
#define RTCNT12 RTCTIM0
#define RTCNT34 RTCTIM1
#define BTSSEL (0x80) /* fBT = fMCLK (main clock) */
#define BTHOLD (0x40) /* BT1 is held if this bit is set */
#define BTDIV (0x20) /* fCLK2 = ACLK:256 */
//#define res (0x10)
//#define res (0x08)
#define BTIP2 (0x04)
#define BTIP1 (0x02)
#define BTIP0 (0x01)
#define RTCBCD (0x80) /* RTC BCD Select */
#define RTCHOLD (0x40) /* RTC Hold */
#define RTCMODE1 (0x20) /* RTC Mode 1 */
#define RTCMODE0 (0x10) /* RTC Mode 0 */
#define RTCTEV1 (0x08) /* RTC Time Event 1 */
#define RTCTEV0 (0x04) /* RTC Time Event 0 */
#define RTCIE (0x02) /* RTC Interrupt Enable */
#define RTCFG (0x01) /* RTC Event Flag */
#define RTCTEV_0 (0x00) /* RTC Time Event: 0 */
#define RTCTEV_1 (0x04) /* RTC Time Event: 1 */
#define RTCTEV_2 (0x08) /* RTC Time Event: 2 */
#define RTCTEV_3 (0x0C) /* RTC Time Event: 3 */
#define RTCMODE_0 (0x00) /* RTC Mode: 0 */
#define RTCMODE_1 (0x10) /* RTC Mode: 1 */
#define RTCMODE_2 (0x20) /* RTC Mode: 2 */
#define RTCMODE_3 (0x30) /* RTC Mode: 3 */
/* Frequency of the BTCNT2 coded with Bit 5 and 7 in BTCTL */
#define BT_fCLK2_ACLK (0x00)
#define BT_fCLK2_ACLK_DIV256 (BTDIV)
#define BT_fCLK2_MCLK (BTSSEL)
/* Interrupt interval time fINT coded with Bits 0-2 in BTCTL */
#define BT_fCLK2_DIV2 (0x00) /* fINT = fCLK2:2 (default) */
#define BT_fCLK2_DIV4 (BTIP0) /* fINT = fCLK2:4 */
#define BT_fCLK2_DIV8 (BTIP1) /* fINT = fCLK2:8 */
#define BT_fCLK2_DIV16 (BTIP1+BTIP0) /* fINT = fCLK2:16 */
#define BT_fCLK2_DIV32 (BTIP2) /* fINT = fCLK2:32 */
#define BT_fCLK2_DIV64 (BTIP2+BTIP0) /* fINT = fCLK2:64 */
#define BT_fCLK2_DIV128 (BTIP2+BTIP1) /* fINT = fCLK2:128 */
#define BT_fCLK2_DIV256 (BTIP2+BTIP1+BTIP0) /* fINT = fCLK2:256 */
/* with assumed vlues of fACLK=32KHz, fMCLK=1MHz */
/* fBT=fACLK is thought for longer interval times */
#define BT_ADLY_0_064 (0x00) /* 0.064ms interval (default) */
#define BT_ADLY_0_125 (BTIP0) /* 0.125ms " */
#define BT_ADLY_0_25 (BTIP1) /* 0.25ms " */
#define BT_ADLY_0_5 (BTIP1+BTIP0) /* 0.5ms " */
#define BT_ADLY_1 (BTIP2) /* 1ms " */
#define BT_ADLY_2 (BTIP2+BTIP0) /* 2ms " */
#define BT_ADLY_4 (BTIP2+BTIP1) /* 4ms " */
#define BT_ADLY_8 (BTIP2+BTIP1+BTIP0) /* 8ms " */
#define BT_ADLY_16 (BTDIV) /* 16ms " */
#define BT_ADLY_32 (BTDIV+BTIP0) /* 32ms " */
#define BT_ADLY_64 (BTDIV+BTIP1) /* 64ms " */
#define BT_ADLY_125 (BTDIV+BTIP1+BTIP0) /* 125ms " */
#define BT_ADLY_250 (BTDIV+BTIP2) /* 250ms " */
#define BT_ADLY_500 (BTDIV+BTIP2+BTIP0) /* 500ms " */
#define BT_ADLY_1000 (BTDIV+BTIP2+BTIP1) /* 1000ms " */
#define BT_ADLY_2000 (BTDIV+BTIP2+BTIP1+BTIP0) /* 2000ms " */
/* fCLK2=fMCLK (1MHz) is thought for short interval times */
/* the timing for short intervals is more precise than ACLK */
/* NOTE */
/* Be sure that the SCFQCTL-Register is set to 01Fh so that fMCLK=1MHz */
/* Too low interval time results in interrupts too frequent for the processor to handle! */
#define BT_MDLY_0_002 (BTSSEL) /* 0.002ms interval *** interval times */
#define BT_MDLY_0_004 (BTSSEL+BTIP0) /* 0.004ms " *** too short for */
#define BT_MDLY_0_008 (BTSSEL+BTIP1) /* 0.008ms " *** interrupt */
#define BT_MDLY_0_016 (BTSSEL+BTIP1+BTIP0) /* 0.016ms " *** handling */
#define BT_MDLY_0_032 (BTSSEL+BTIP2) /* 0.032ms " */
#define BT_MDLY_0_064 (BTSSEL+BTIP2+BTIP0) /* 0.064ms " */
#define BT_MDLY_0_125 (BTSSEL+BTIP2+BTIP1) /* 0.125ms " */
#define BT_MDLY_0_25 (BTSSEL+BTIP2+BTIP1+BTIP0)/* 0.25ms " */
/* Hold coded with Bits 6-7 in BT(1)CTL */
/* this is for BT */
#define BTHOLD_CNT1 (BTHOLD) /* BTCNT1 is held while BTHOLD is set */
#define BTHOLD_CNT1_2 (BTHOLD+BTDIV) /* BT1CNT1 .AND. BT1CNT2 are held while ~ is set */
/* INTERRUPT CONTROL BITS */
/* #define BTIE 0x80 */
/* #define BTIFG 0x80 */
/************************************************************
* Comparator A
************************************************************/
#define __MSP430_HAS_COMPA__ /* Definition to show that Module is available */
#define CACTL1_ (0x0059) /* Comparator A Control 1 */
DEFC( CACTL1 , CACTL1_)
#define CACTL2_ (0x005A) /* Comparator A Control 2 */
DEFC( CACTL2 , CACTL2_)
#define CAPD_ (0x005B) /* Comparator A Port Disable */
DEFC( CAPD , CAPD_)
#define CAIFG (0x01) /* Comp. A Interrupt Flag */
#define CAIE (0x02) /* Comp. A Interrupt Enable */
#define CAIES (0x04) /* Comp. A Int. Edge Select: 0:rising / 1:falling */
#define CAON (0x08) /* Comp. A enable */
#define CAREF0 (0x10) /* Comp. A Internal Reference Select 0 */
#define CAREF1 (0x20) /* Comp. A Internal Reference Select 1 */
#define CARSEL (0x40) /* Comp. A Internal Reference Enable */
#define CAEX (0x80) /* Comp. A Exchange Inputs */
#define CAREF_0 (0x00) /* Comp. A Int. Ref. Select 0 : Off */
#define CAREF_1 (0x10) /* Comp. A Int. Ref. Select 1 : 0.25*Vcc */
#define CAREF_2 (0x20) /* Comp. A Int. Ref. Select 2 : 0.5*Vcc */
#define CAREF_3 (0x30) /* Comp. A Int. Ref. Select 3 : Vt*/
#define CAOUT (0x01) /* Comp. A Output */
#define CAF (0x02) /* Comp. A Enable Output Filter */
#define P2CA0 (0x04) /* Comp. A Connect External Signal to CA0 : 1 */
#define P2CA1 (0x08) /* Comp. A Connect External Signal to CA1 : 1 */
#define CACTL24 (0x10)
#define CACTL25 (0x20)
#define CACTL26 (0x40)
#define CACTL27 (0x80)
#define CAPD0 (0x01) /* Comp. A Disable Input Buffer of Port Register .0 */
#define CAPD1 (0x02) /* Comp. A Disable Input Buffer of Port Register .1 */
#define CAPD2 (0x04) /* Comp. A Disable Input Buffer of Port Register .2 */
#define CAPD3 (0x08) /* Comp. A Disable Input Buffer of Port Register .3 */
#define CAPD4 (0x10) /* Comp. A Disable Input Buffer of Port Register .4 */
#define CAPD5 (0x20) /* Comp. A Disable Input Buffer of Port Register .5 */
#define CAPD6 (0x40) /* Comp. A Disable Input Buffer of Port Register .6 */
#define CAPD7 (0x80) /* Comp. A Disable Input Buffer of Port Register .7 */
/************************************************************
* DAC12
************************************************************/
#define __MSP430_HAS_DAC12_2__ /* Definition to show that Module is available */
#define DAC12_0CTL_ (0x01c0) /* DAC12_0 Control */
DEFW( DAC12_0CTL , DAC12_0CTL_)
#define DAC12_1CTL_ (0x01c2) /* DAC12_1 Control */
DEFW( DAC12_1CTL , DAC12_1CTL_)
#define DAC12GRP (0x0001) /* DAC12 group */
#define DAC12ENC (0x0002) /* DAC12 enable conversion */
#define DAC12IFG (0x0004) /* DAC12 interrupt flag */
#define DAC12IE (0x0008) /* DAC12 interrupt enable */
#define DAC12DF (0x0010) /* DAC12 data format */
#define DAC12AMP0 (0x0020) /* DAC12 amplifier bit 0 */
#define DAC12AMP1 (0x0040) /* DAC12 amplifier bit 1 */
#define DAC12AMP2 (0x0080) /* DAC12 amplifier bit 2 */
#define DAC12IR (0x0100) /* DAC12 input reference and output range */
#define DAC12CALON (0x0200) /* DAC12 calibration */
#define DAC12LSEL0 (0x0400) /* DAC12 load select bit 0 */
#define DAC12LSEL1 (0x0800) /* DAC12 load select bit 1 */
#define DAC12RES (0x1000) /* DAC12 resolution */
#define DAC12SREF0 (0x2000) /* DAC12 reference bit 0 */
#define DAC12SREF1 (0x4000) /* DAC12 reference bit 1 */
#define DAC12OPS (0x8000) /* DAC12 Operation Amp. */
#define DAC12AMP_0 (0*0x0020u) /* DAC12 amplifier 0: off, 3-state */
#define DAC12AMP_1 (1*0x0020u) /* DAC12 amplifier 1: off, off */
#define DAC12AMP_2 (2*0x0020u) /* DAC12 amplifier 2: low, low */
#define DAC12AMP_3 (3*0x0020u) /* DAC12 amplifier 3: low, medium */
#define DAC12AMP_4 (4*0x0020u) /* DAC12 amplifier 4: low, high */
#define DAC12AMP_5 (5*0x0020u) /* DAC12 amplifier 5: medium, medium */
#define DAC12AMP_6 (6*0x0020u) /* DAC12 amplifier 6: medium, high */
#define DAC12AMP_7 (7*0x0020u) /* DAC12 amplifier 7: high, high */
#define DAC12LSEL_0 (0*0x0400u) /* DAC12 load select 0: direct */
#define DAC12LSEL_1 (1*0x0400u) /* DAC12 load select 1: latched with DAT */
#define DAC12LSEL_2 (2*0x0400u) /* DAC12 load select 2: latched with pos. Timer_A3.OUT1 */
#define DAC12LSEL_3 (3*0x0400u) /* DAC12 load select 3: latched with pos. Timer_B7.OUT1 */
#define DAC12SREF_0 (0*0x2000u) /* DAC12 reference 0: Vref+ */
#define DAC12SREF_1 (1*0x2000u) /* DAC12 reference 1: Vref+ */
#define DAC12SREF_2 (2*0x2000u) /* DAC12 reference 2: Veref+ */
#define DAC12SREF_3 (3*0x2000u) /* DAC12 reference 3: Veref+ */
#define DAC12_0DAT_ (0x01c8) /* DAC12_0 Data */
DEFW( DAC12_0DAT , DAC12_0DAT_)
#define DAC12_1DAT_ (0x01ca) /* DAC12_1 Data */
DEFW( DAC12_1DAT , DAC12_1DAT_)
/************************************************************
* DMA_X
************************************************************/
#define __MSP430_HAS_DMAX_3__ /* Definition to show that Module is available */
#define DMACTL0_ (0x0122) /* DMA Module Control 0 */
DEFW( DMACTL0 , DMACTL0_)
#define DMA0TSEL0 (0x0001) /* DMA channel 0 transfer select bit 0 */
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