📄 msp430xg46x.h
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#define ADC12MCTL4_ (0x0084) /* ADC12 Memory Control 4 */
DEFC( ADC12MCTL4 , ADC12MCTL4_)
#define ADC12MCTL5_ (0x0085) /* ADC12 Memory Control 5 */
DEFC( ADC12MCTL5 , ADC12MCTL5_)
#define ADC12MCTL6_ (0x0086) /* ADC12 Memory Control 6 */
DEFC( ADC12MCTL6 , ADC12MCTL6_)
#define ADC12MCTL7_ (0x0087) /* ADC12 Memory Control 7 */
DEFC( ADC12MCTL7 , ADC12MCTL7_)
#define ADC12MCTL8_ (0x0088) /* ADC12 Memory Control 8 */
DEFC( ADC12MCTL8 , ADC12MCTL8_)
#define ADC12MCTL9_ (0x0089) /* ADC12 Memory Control 9 */
DEFC( ADC12MCTL9 , ADC12MCTL9_)
#define ADC12MCTL10_ (0x008A) /* ADC12 Memory Control 10 */
DEFC( ADC12MCTL10 , ADC12MCTL10_)
#define ADC12MCTL11_ (0x008B) /* ADC12 Memory Control 11 */
DEFC( ADC12MCTL11 , ADC12MCTL11_)
#define ADC12MCTL12_ (0x008C) /* ADC12 Memory Control 12 */
DEFC( ADC12MCTL12 , ADC12MCTL12_)
#define ADC12MCTL13_ (0x008D) /* ADC12 Memory Control 13 */
DEFC( ADC12MCTL13 , ADC12MCTL13_)
#define ADC12MCTL14_ (0x008E) /* ADC12 Memory Control 14 */
DEFC( ADC12MCTL14 , ADC12MCTL14_)
#define ADC12MCTL15_ (0x008F) /* ADC12 Memory Control 15 */
DEFC( ADC12MCTL15 , ADC12MCTL15_)
/* ADC12CTL0 */
#define ADC12SC (0x001) /* ADC12 Start Conversion */
#define ENC (0x002) /* ADC12 Enable Conversion */
#define ADC12TOVIE (0x004) /* ADC12 Timer Overflow interrupt enable */
#define ADC12OVIE (0x008) /* ADC12 Overflow interrupt enable */
#define ADC12ON (0x010) /* ADC12 On/enable */
#define REFON (0x020) /* ADC12 Reference on */
#define REF2_5V (0x040) /* ADC12 Ref 0:1.5V / 1:2.5V */
#define MSC (0x080) /* ADC12 Multiple SampleConversion */
#define SHT00 (0x0100) /* ADC12 Sample Hold 0 Select 0 */
#define SHT01 (0x0200) /* ADC12 Sample Hold 0 Select 1 */
#define SHT02 (0x0400) /* ADC12 Sample Hold 0 Select 2 */
#define SHT03 (0x0800) /* ADC12 Sample Hold 0 Select 3 */
#define SHT10 (0x1000) /* ADC12 Sample Hold 0 Select 0 */
#define SHT11 (0x2000) /* ADC12 Sample Hold 1 Select 1 */
#define SHT12 (0x4000) /* ADC12 Sample Hold 2 Select 2 */
#define SHT13 (0x8000) /* ADC12 Sample Hold 3 Select 3 */
#define MSH (0x080)
#define SHT0_0 (0*0x100u)
#define SHT0_1 (1*0x100u)
#define SHT0_2 (2*0x100u)
#define SHT0_3 (3*0x100u)
#define SHT0_4 (4*0x100u)
#define SHT0_5 (5*0x100u)
#define SHT0_6 (6*0x100u)
#define SHT0_7 (7*0x100u)
#define SHT0_8 (8*0x100u)
#define SHT0_9 (9*0x100u)
#define SHT0_10 (10*0x100u)
#define SHT0_11 (11*0x100u)
#define SHT0_12 (12*0x100u)
#define SHT0_13 (13*0x100u)
#define SHT0_14 (14*0x100u)
#define SHT0_15 (15*0x100u)
#define SHT1_0 (0*0x1000u)
#define SHT1_1 (1*0x1000u)
#define SHT1_2 (2*0x1000u)
#define SHT1_3 (3*0x1000u)
#define SHT1_4 (4*0x1000u)
#define SHT1_5 (5*0x1000u)
#define SHT1_6 (6*0x1000u)
#define SHT1_7 (7*0x1000u)
#define SHT1_8 (8*0x1000u)
#define SHT1_9 (9*0x1000u)
#define SHT1_10 (10*0x1000u)
#define SHT1_11 (11*0x1000u)
#define SHT1_12 (12*0x1000u)
#define SHT1_13 (13*0x1000u)
#define SHT1_14 (14*0x1000u)
#define SHT1_15 (15*0x1000u)
/* ADC12CTL1 */
#define ADC12BUSY (0x0001) /* ADC12 Busy */
#define CONSEQ0 (0x0002) /* ADC12 Conversion Sequence Select 0 */
#define CONSEQ1 (0x0004) /* ADC12 Conversion Sequence Select 1 */
#define ADC12SSEL0 (0x0008) /* ADC12 Clock Source Select 0 */
#define ADC12SSEL1 (0x0010) /* ADC12 Clock Source Select 1 */
#define ADC12DIV0 (0x0020) /* ADC12 Clock Divider Select 0 */
#define ADC12DIV1 (0x0040) /* ADC12 Clock Divider Select 1 */
#define ADC12DIV2 (0x0080) /* ADC12 Clock Divider Select 2 */
#define ISSH (0x0100) /* ADC12 Invert Sample Hold Signal */
#define SHP (0x0200) /* ADC12 Sample/Hold Pulse Mode */
#define SHS0 (0x0400) /* ADC12 Sample/Hold Source 0 */
#define SHS1 (0x0800) /* ADC12 Sample/Hold Source 1 */
#define CSTARTADD0 (0x1000) /* ADC12 Conversion Start Address 0 */
#define CSTARTADD1 (0x2000) /* ADC12 Conversion Start Address 1 */
#define CSTARTADD2 (0x4000) /* ADC12 Conversion Start Address 2 */
#define CSTARTADD3 (0x8000) /* ADC12 Conversion Start Address 3 */
#define CONSEQ_0 (0*2u)
#define CONSEQ_1 (1*2u)
#define CONSEQ_2 (2*2u)
#define CONSEQ_3 (3*2u)
#define ADC12SSEL_0 (0*8u)
#define ADC12SSEL_1 (1*8u)
#define ADC12SSEL_2 (2*8u)
#define ADC12SSEL_3 (3*8u)
#define ADC12DIV_0 (0*0x20u)
#define ADC12DIV_1 (1*0x20u)
#define ADC12DIV_2 (2*0x20u)
#define ADC12DIV_3 (3*0x20u)
#define ADC12DIV_4 (4*0x20u)
#define ADC12DIV_5 (5*0x20u)
#define ADC12DIV_6 (6*0x20u)
#define ADC12DIV_7 (7*0x20u)
#define SHS_0 (0*0x400u)
#define SHS_1 (1*0x400u)
#define SHS_2 (2*0x400u)
#define SHS_3 (3*0x400u)
#define CSTARTADD_0 (0*0x1000u)
#define CSTARTADD_1 (1*0x1000u)
#define CSTARTADD_2 (2*0x1000u)
#define CSTARTADD_3 (3*0x1000u)
#define CSTARTADD_4 (4*0x1000u)
#define CSTARTADD_5 (5*0x1000u)
#define CSTARTADD_6 (6*0x1000u)
#define CSTARTADD_7 (7*0x1000u)
#define CSTARTADD_8 (8*0x1000u)
#define CSTARTADD_9 (9*0x1000u)
#define CSTARTADD_10 (10*0x1000u)
#define CSTARTADD_11 (11*0x1000u)
#define CSTARTADD_12 (12*0x1000u)
#define CSTARTADD_13 (13*0x1000u)
#define CSTARTADD_14 (14*0x1000u)
#define CSTARTADD_15 (15*0x1000u)
/* ADC12MCTLx */
#define INCH0 (0x0001) /* ADC12 Input Channel Select Bit 0 */
#define INCH1 (0x0002) /* ADC12 Input Channel Select Bit 1 */
#define INCH2 (0x0004) /* ADC12 Input Channel Select Bit 2 */
#define INCH3 (0x0008) /* ADC12 Input Channel Select Bit 3 */
#define SREF0 (0x0010) /* ADC12 Select Reference Bit 0 */
#define SREF1 (0x0020) /* ADC12 Select Reference Bit 1 */
#define SREF2 (0x0040) /* ADC12 Select Reference Bit 2 */
#define EOS (0x0080) /* ADC12 End of Sequence */
#define INCH_0 (0)
#define INCH_1 (1)
#define INCH_2 (2)
#define INCH_3 (3)
#define INCH_4 (4)
#define INCH_5 (5)
#define INCH_6 (6)
#define INCH_7 (7)
#define INCH_8 (8)
#define INCH_9 (9)
#define INCH_10 (10)
#define INCH_11 (11)
#define INCH_12 (12)
#define INCH_13 (13)
#define INCH_14 (14)
#define INCH_15 (15)
#define SREF_0 (0*0x10u)
#define SREF_1 (1*0x10u)
#define SREF_2 (2*0x10u)
#define SREF_3 (3*0x10u)
#define SREF_4 (4*0x10u)
#define SREF_5 (5*0x10u)
#define SREF_6 (6*0x10u)
#define SREF_7 (7*0x10u)
/* ADC12IV Definitions */
#define ADC12IV_NONE (0x0000) /* No Interrupt pending */
#define ADC12IV_ADC12OVIFG (0x0002) /* ADC12OVIFG */
#define ADC12IV_ADC12TOVIFG (0x0004) /* ADC12TOVIFG */
#define ADC12IV_ADC12IFG0 (0x0006) /* ADC12IFG0 */
#define ADC12IV_ADC12IFG1 (0x0008) /* ADC12IFG1 */
#define ADC12IV_ADC12IFG2 (0x000A) /* ADC12IFG2 */
#define ADC12IV_ADC12IFG3 (0x000C) /* ADC12IFG3 */
#define ADC12IV_ADC12IFG4 (0x000E) /* ADC12IFG4 */
#define ADC12IV_ADC12IFG5 (0x0010) /* ADC12IFG5 */
#define ADC12IV_ADC12IFG6 (0x0012) /* ADC12IFG6 */
#define ADC12IV_ADC12IFG7 (0x0014) /* ADC12IFG7 */
#define ADC12IV_ADC12IFG8 (0x0016) /* ADC12IFG8 */
#define ADC12IV_ADC12IFG9 (0x0018) /* ADC12IFG9 */
#define ADC12IV_ADC12IFG10 (0x001A) /* ADC12IFG10 */
#define ADC12IV_ADC12IFG11 (0x001C) /* ADC12IFG11 */
#define ADC12IV_ADC12IFG12 (0x001E) /* ADC12IFG12 */
#define ADC12IV_ADC12IFG13 (0x0020) /* ADC12IFG13 */
#define ADC12IV_ADC12IFG14 (0x0022) /* ADC12IFG14 */
#define ADC12IV_ADC12IFG15 (0x0024) /* ADC12IFG15 */
/************************************************************
* BASIC TIMER with Real Time Clock
************************************************************/
#define __MSP430_HAS_BT_RTC__ /* Definition to show that Module is available */
#define BTCTL_ (0x0040) /* Basic Timer Control */
#ifndef __IAR_SYSTEMS_ICC__
DEFC( BTCTL , BTCTL_)
#endif
#define RTCCTL_ (0x0041) /* Real Time Clock Control */
#ifndef __IAR_SYSTEMS_ICC__
DEFC( RTCCTL , RTCCTL_)
#endif
#define RTCNT1_ (0x0042) /* Real Time Counter 1 */
#ifndef __IAR_SYSTEMS_ICC__
DEFC( RTCNT1 , RTCNT1_)
#endif
#define RTCNT2_ (0x0043) /* Real Time Counter 2 */
#ifndef __IAR_SYSTEMS_ICC__
DEFC( RTCNT2 , RTCNT2_)
#endif
#define RTCNT3_ (0x0044) /* Real Time Counter 3 */
#ifndef __IAR_SYSTEMS_ICC__
DEFC( RTCNT3 , RTCNT3_)
#endif
#define RTCNT4_ (0x0045) /* Real Time Counter 4 */
#ifndef __IAR_SYSTEMS_ICC__
DEFC( RTCNT4 , RTCNT4_)
#endif
#define BTCNT1_ (0x0046) /* Basic Timer Count 1 */
#ifndef __IAR_SYSTEMS_ICC__
DEFC( BTCNT1 , BTCNT1_)
#endif
#define BTCNT2_ (0x0047) /* Basic Timer Count 2 */
#ifndef __IAR_SYSTEMS_ICC__
DEFC( BTCNT2 , BTCNT2_)
#endif
#define RTCDAY_ (0x004C) /* Real Time Clock Day */
#ifndef __IAR_SYSTEMS_ICC__
DEFC( RTCDAY , RTCDAY_)
#endif
#define RTCMON_ (0x004D) /* Real Time Clock Month */
#ifndef __IAR_SYSTEMS_ICC__
DEFC( RTCMON , RTCMON_)
#endif
#define RTCYEARL_ (0x004E) /* Real Time Clock Year (Low Byte) */
#ifndef __IAR_SYSTEMS_ICC__
DEFC( RTCYEARL , RTCYEARL_)
#endif
#define RTCYEARH_ (0x004F) /* Real Time Clock Year (High Byte) */
#ifndef __IAR_SYSTEMS_ICC__
DEFC( RTCYEARH , RTCYEARH_)
#endif
#define RTCSEC RTCNT1
#define RTCMIN RTCNT2
#define RTCHOUR RTCNT3
#define RTCDOW RTCNT4
#define RTCTL_ (0x0040) /* Basic/Real Timer Control */
#ifndef __IAR_SYSTEMS_ICC__
DEFW( RTCTL , RTCTL_)
#endif
#ifdef __IAR_SYSTEMS_ICC__
__no_init union
{
struct
{
DEFXC BTCTL;
DEFXC RTCCTL;
};
DEFXW RTCTL;
} @ 0x0040;
#endif
#define RTCTIM0_ (0x0042) /* Real Time Clock Time 0 */
#ifndef __IAR_SYSTEMS_ICC__
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