📄 msp430xg46x.h
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/********************************************************************
*
* Standard register and bit definitions for the Texas Instruments
* MSP430 microcontroller.
*
* This file supports assembler and C development for
* MSP430xG46x devices.
*
* Texas Instruments, Version 1.7
*
* Rev. 1.0, Setup
* Rev. 1.1, Fixed Names for USCI an settings for DMA
* Rev. 1.2, Added VLD bits in SVS module
* Rev. 1.3, Removed definitions for BTRESET
* Fixed swapped definition of RTCxxx
* Rev. 1.4, Removed unused ME1 definition
* Rev. 1.5, added definitions for Interrupt Vectors xxIV
* Rev. 1.6, changed 'void __data20 * volatile' definition
* Rev. 1.6, added LFXT1DIG
*
*
********************************************************************/
#ifndef __msp430xG46x
#define __msp430xG46x
#ifdef __IAR_SYSTEMS_ICC__
#ifndef _SYSTEM_BUILD
#pragma system_include
#endif
#endif
#if (((__TID__ >> 8) & 0x7F) != 0x2b) /* 0x2b = 43 dec */
#error msp430xG46x.h file for use with ICC430/A430 only
#endif
#ifdef __IAR_SYSTEMS_ICC__
#include <in430.h>
#pragma language=extended
#define DEFC(name, address) __no_init volatile unsigned char name @ address;
#define DEFW(name, address) __no_init volatile unsigned short name @ address;
#if __REGISTER_MODEL__ == __REGISTER_MODEL_REG20__
#define DEFA(name, address) __no_init void __data20 * volatile name @ address;
#else
#define DEFA(name, address) __no_init volatile unsigned long name @ address;
#endif
#define DEFXC volatile unsigned char
#define DEFXW volatile unsigned short
#if __REGISTER_MODEL__ == __REGISTER_MODEL_REG20__
#define DEFXA void __data20 * volatile
#else
#define DEFXA volatile unsigned long
#endif
#endif /* __IAR_SYSTEMS_ICC__ */
#ifdef __IAR_SYSTEMS_ASM__
#define DEFC(name, address) sfrb name = address;
#define DEFW(name, address) sfrw name = address;
#define DEFA(name, address) sfrl name = address;
#endif /* __IAR_SYSTEMS_ASM__*/
#ifdef __cplusplus
#define READ_ONLY
#else
#define READ_ONLY const
#endif
/************************************************************
* STANDARD BITS
************************************************************/
#define BIT0 (0x0001)
#define BIT1 (0x0002)
#define BIT2 (0x0004)
#define BIT3 (0x0008)
#define BIT4 (0x0010)
#define BIT5 (0x0020)
#define BIT6 (0x0040)
#define BIT7 (0x0080)
#define BIT8 (0x0100)
#define BIT9 (0x0200)
#define BITA (0x0400)
#define BITB (0x0800)
#define BITC (0x1000)
#define BITD (0x2000)
#define BITE (0x4000)
#define BITF (0x8000)
/************************************************************
* STATUS REGISTER BITS
************************************************************/
#define C (0x0001)
#define Z (0x0002)
#define N (0x0004)
#define V (0x0100)
#define GIE (0x0008)
#define CPUOFF (0x0010)
#define OSCOFF (0x0020)
#define SCG0 (0x0040)
#define SCG1 (0x0080)
/* Low Power Modes coded with Bits 4-7 in SR */
#ifndef __IAR_SYSTEMS_ICC /* Begin #defines for assembler */
#define LPM0 (CPUOFF)
#define LPM1 (SCG0+CPUOFF)
#define LPM2 (SCG1+CPUOFF)
#define LPM3 (SCG1+SCG0+CPUOFF)
#define LPM4 (SCG1+SCG0+OSCOFF+CPUOFF)
/* End #defines for assembler */
#else /* Begin #defines for C */
#define LPM0_bits (CPUOFF)
#define LPM1_bits (SCG0+CPUOFF)
#define LPM2_bits (SCG1+CPUOFF)
#define LPM3_bits (SCG1+SCG0+CPUOFF)
#define LPM4_bits (SCG1+SCG0+OSCOFF+CPUOFF)
#include <In430.h>
#define LPM0 _BIS_SR(LPM0_bits) /* Enter Low Power Mode 0 */
#define LPM0_EXIT _BIC_SR_IRQ(LPM0_bits) /* Exit Low Power Mode 0 */
#define LPM1 _BIS_SR(LPM1_bits) /* Enter Low Power Mode 1 */
#define LPM1_EXIT _BIC_SR_IRQ(LPM1_bits) /* Exit Low Power Mode 1 */
#define LPM2 _BIS_SR(LPM2_bits) /* Enter Low Power Mode 2 */
#define LPM2_EXIT _BIC_SR_IRQ(LPM2_bits) /* Exit Low Power Mode 2 */
#define LPM3 _BIS_SR(LPM3_bits) /* Enter Low Power Mode 3 */
#define LPM3_EXIT _BIC_SR_IRQ(LPM3_bits) /* Exit Low Power Mode 3 */
#define LPM4 _BIS_SR(LPM4_bits) /* Enter Low Power Mode 4 */
#define LPM4_EXIT _BIC_SR_IRQ(LPM4_bits) /* Exit Low Power Mode 4 */
#endif /* End #defines for C */
/************************************************************
* CPU
************************************************************/
#define __MSP430_HAS_MSP430X_CPU__ /* Definition to show that it has MSP430X CPU */
/************************************************************
* PERIPHERAL FILE MAP
************************************************************/
/************************************************************
* SPECIAL FUNCTION REGISTER ADDRESSES + CONTROL BITS
************************************************************/
#define IE1_ (0x0000) /* Interrupt Enable 1 */
DEFC( IE1 , IE1_)
#define WDTIE (0x01)
#define OFIE (0x02)
#define NMIIE (0x10)
#define ACCVIE (0x20)
#define IFG1_ (0x0002) /* Interrupt Flag 1 */
DEFC( IFG1 , IFG1_)
#define WDTIFG (0x01)
#define OFIFG (0x02)
#define NMIIFG (0x10)
#define IE2_ (0x0001) /* Interrupt Enable 2 */
DEFC( IE2 , IE2_)
#define U1IE IE2 /* UART1 Interrupt Enable Register */
#define UC0IE IE2
#define UCA0RXIE (0x01)
#define UCA0TXIE (0x02)
#define UCB0RXIE (0x04)
#define UCB0TXIE (0x08)
#define URXIE1 (0x10)
#define UTXIE1 (0x20)
#define BTIE (0x80)
#define IFG2_ (0x0003) /* Interrupt Flag 2 */
DEFC( IFG2 , IFG2_)
#define U1IFG IFG2 /* UART1 Interrupt Flag Register */
#define UC0IFG IFG2
#define UCA0RXIFG (0x01)
#define UCA0TXIFG (0x02)
#define UCB0RXIFG (0x04)
#define UCB0TXIFG (0x08)
#define URXIFG1 (0x10)
#define UTXIFG1 (0x20)
#define BTIFG (0x80)
#define ME2_ (0x0005) /* Module Enable 2 */
DEFC( ME2 , ME2_)
#define U1ME ME2 /* UART1 Module Enable Register */
#define URXE1 (0x10)
#define UTXE1 (0x20)
#define USPIE1 (0x10)
/************************************************************
* ADC12
************************************************************/
#define __MSP430_HAS_ADC12__ /* Definition to show that Module is available */
#define ADC12CTL0_ (0x01A0) /* ADC12 Control 0 */
DEFW( ADC12CTL0 , ADC12CTL0_)
#define ADC12CTL1_ (0x01A2) /* ADC12 Control 1 */
DEFW( ADC12CTL1 , ADC12CTL1_)
#define ADC12IFG_ (0x01A4) /* ADC12 Interrupt Flag */
DEFW( ADC12IFG , ADC12IFG_)
#define ADC12IE_ (0x01A6) /* ADC12 Interrupt Enable */
DEFW( ADC12IE , ADC12IE_)
#define ADC12IV_ (0x01A8) /* ADC12 Interrupt Vector Word */
DEFW( ADC12IV , ADC12IV_)
#define ADC12MEM_ (0x0140) /* ADC12 Conversion Memory */
#ifndef __IAR_SYSTEMS_ICC
#define ADC12MEM (ADC12MEM_) /* ADC12 Conversion Memory (for assembler) */
#else
#define ADC12MEM ((int*) ADC12MEM_) /* ADC12 Conversion Memory (for C) */
#endif
#define ADC12MEM0_ (0x0140) /* ADC12 Conversion Memory 0 */
DEFW( ADC12MEM0 , ADC12MEM0_)
#define ADC12MEM1_ (0x0142) /* ADC12 Conversion Memory 1 */
DEFW( ADC12MEM1 , ADC12MEM1_)
#define ADC12MEM2_ (0x0144) /* ADC12 Conversion Memory 2 */
DEFW( ADC12MEM2 , ADC12MEM2_)
#define ADC12MEM3_ (0x0146) /* ADC12 Conversion Memory 3 */
DEFW( ADC12MEM3 , ADC12MEM3_)
#define ADC12MEM4_ (0x0148) /* ADC12 Conversion Memory 4 */
DEFW( ADC12MEM4 , ADC12MEM4_)
#define ADC12MEM5_ (0x014A) /* ADC12 Conversion Memory 5 */
DEFW( ADC12MEM5 , ADC12MEM5_)
#define ADC12MEM6_ (0x014C) /* ADC12 Conversion Memory 6 */
DEFW( ADC12MEM6 , ADC12MEM6_)
#define ADC12MEM7_ (0x014E) /* ADC12 Conversion Memory 7 */
DEFW( ADC12MEM7 , ADC12MEM7_)
#define ADC12MEM8_ (0x0150) /* ADC12 Conversion Memory 8 */
DEFW( ADC12MEM8 , ADC12MEM8_)
#define ADC12MEM9_ (0x0152) /* ADC12 Conversion Memory 9 */
DEFW( ADC12MEM9 , ADC12MEM9_)
#define ADC12MEM10_ (0x0154) /* ADC12 Conversion Memory 10 */
DEFW( ADC12MEM10 , ADC12MEM10_)
#define ADC12MEM11_ (0x0156) /* ADC12 Conversion Memory 11 */
DEFW( ADC12MEM11 , ADC12MEM11_)
#define ADC12MEM12_ (0x0158) /* ADC12 Conversion Memory 12 */
DEFW( ADC12MEM12 , ADC12MEM12_)
#define ADC12MEM13_ (0x015A) /* ADC12 Conversion Memory 13 */
DEFW( ADC12MEM13 , ADC12MEM13_)
#define ADC12MEM14_ (0x015C) /* ADC12 Conversion Memory 14 */
DEFW( ADC12MEM14 , ADC12MEM14_)
#define ADC12MEM15_ (0x015E) /* ADC12 Conversion Memory 15 */
DEFW( ADC12MEM15 , ADC12MEM15_)
#define ADC12MCTL_ (0x0080) /* ADC12 Memory Control */
#ifndef __IAR_SYSTEMS_ICC
#define ADC12MCTL (ADC12MCTL_) /* ADC12 Memory Control (for assembler) */
#else
#define ADC12MCTL ((char*) ADC12MCTL_) /* ADC12 Memory Control (for C) */
#endif
#define ADC12MCTL0_ (0x0080) /* ADC12 Memory Control 0 */
DEFC( ADC12MCTL0 , ADC12MCTL0_)
#define ADC12MCTL1_ (0x0081) /* ADC12 Memory Control 1 */
DEFC( ADC12MCTL1 , ADC12MCTL1_)
#define ADC12MCTL2_ (0x0082) /* ADC12 Memory Control 2 */
DEFC( ADC12MCTL2 , ADC12MCTL2_)
#define ADC12MCTL3_ (0x0083) /* ADC12 Memory Control 3 */
DEFC( ADC12MCTL3 , ADC12MCTL3_)
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