int_proc.h

本程序为ST公司开发的源代码

  accu1 = hfldec * c[8] + c[9] * hflpf;
  hflpf = accu1;

  if (accu1 > fok_thr)
  {
    counter_down = fok_tdn;
    if (counter_up > 0)
    {
      counter_up -= 1;
    }
    else
    {
      fok = 0x1;
    }
  }
  else
  {
    counter_up = fok_tup;
    if (counter_down > 0)
    {
      counter_down -= 1;
    }
    else
    {
      fok = 0x0;
    }
  }

  /* downsampling of internal signals */
#if ((1 == OPTIMIZED_DEC) && (1 == HARDWARE_LOOP))

  ax0 = SIGDEC_VAR_ARRAY_ADD;
  ay0 = SIG_ARRAY_ADD;

  dx1 = *ay0++;                 /* sig[0] */
  dy0_int = 0x0002;

  accu0 = dx1 >> dy0_int;       /* sig[0] >> 2 */

  loop(7)
  {
    dx0 = *ax0;                 /* sigdec_var[i] */

    accu0 = accu0 + dx0;        /* sigdec_var[i] + sig[i] >> 2 */
    dx1 = *ay0++;               /* sig[i+1] */

    *ax0++ = accu0;             /* sigdec_var[i] += sig[i] >> 2 */
    accu0 = dx1 >> dy0_int;     /* sig[i+1] >> 2 */
  }
#elif (1 == OPTIMIZED_DEC)
  ax0 = SIGDEC_VAR_ARRAY_ADD;
  ay0 = SIG_ARRAY_ADD;

  dx1 = *ay0++;                 /* sig[0] */
  dy0_int = 0x0002;

  accu0 = dx1 >> dy0_int;       /* sig[0] >> 2 */

  /***** i = 0 *****/
  dx0 = *ax0;                   /* sigdec_var[i] */

  accu0 = accu0 + dx0;          /* sigdec_var[i] + sig[i] >> 2 */
  dx1 = *ay0++;                 /* sig[i+1] */

  *ax0++ = accu0;               /* sigdec_var[i] += sig[i] >> 2 */
  accu0 = dx1 >> dy0_int;       /* sig[i+1] >> 2 */

  /***** i = 1 *****/
  dx0 = *ax0;                   /* sigdec_var[i] */

  accu0 = accu0 + dx0;          /* sigdec_var[i] + sig[i] >> 2 */
  dx1 = *ay0++;                 /* sig[i+1] */

  *ax0++ = accu0;               /* sigdec_var[i] += sig[i] >> 2 */
  accu0 = dx1 >> dy0_int;       /* sig[i+1] >> 2 */

  /***** i = 2 *****/
  dx0 = *ax0;                   /* sigdec_var[i] */

  accu0 = accu0 + dx0;          /* sigdec_var[i] + sig[i] >> 2 */
  dx1 = *ay0++;                 /* sig[i+1] */

  *ax0++ = accu0;               /* sigdec_var[i] += sig[i] >> 2 */
  accu0 = dx1 >> dy0_int;       /* sig[i+1] >> 2 */

  /***** i = 3 *****/
  dx0 = *ax0;                   /* sigdec_var[i] */

  accu0 = accu0 + dx0;          /* sigdec_var[i] + sig[i] >> 2 */
  dx1 = *ay0++;                 /* sig[i+1] */

  *ax0++ = accu0;               /* sigdec_var[i] += sig[i] >> 2 */
  accu0 = dx1 >> dy0_int;       /* sig[i+1] >> 2 */

  /***** i = 4 *****/
  dx0 = *ax0;                   /* sigdec_var[i] */

  accu0 = accu0 + dx0;          /* sigdec_var[i] + sig[i] >> 2 */
  dx1 = *ay0++;                 /* sig[i+1] */

  *ax0++ = accu0;               /* sigdec_var[i] += sig[i] >> 2 */
  accu0 = dx1 >> dy0_int;       /* sig[i+1] >> 2 */

  /***** i = 5 *****/
  dx0 = *ax0;                   /* sigdec_var[i] */

  accu0 = accu0 + dx0;          /* sigdec_var[i] + sig[i] >> 2 */
  dx1 = *ay0++;                 /* sig[i+1] */

  *ax0++ = accu0;               /* sigdec_var[i] += sig[i] >> 2 */
  accu0 = dx1 >> dy0_int;       /* sig[i+1] >> 2 */

  /***** i = 6 *****/
  dx0 = *ax0;                   /* sigdec_var[i] */

  accu0 = accu0 + dx0;          /* sigdec_var[i] + sig[i] >> 2 */
/*  dx1 = *ay0++; */            /* sig[i+1] */

  *ax0++ = accu0;               /* sigdec_var[i] += sig[i] >> 2 */
/*  accu0 = dx1 >> dy0_int; */  /* sig[i+1] >> 2 */
#else
  fedec_var += (fe >> 2);
  tedec_var += (te >> 2);
  fadec_var += (fa >> 2);
  fa2dec_var += (fa2 >> 2);
  tadec_var += (ta >> 2);
  ta2dec_var += (ta2 >> 2);
  hfldec_var += (hfl >> 2);
#endif

  goto END_SWITCH3;
CASE_33:
/* MR041215 - BEGIN */
  if (!(disc_mode & DISC_MODE_UPDATED))
  {
    disc_mode_int = disc_mode;
    disc_mode |= DISC_MODE_UPDATED;
    dsp_state = get_clr_ttm_speed_ok(dsp_state);
    sw_time = 0;                          /* React immediately on mode change */ /* MR20050106b */
  }

  /* Read CLV buffer level. */
  loop(1) dx0 = CLV1; /* Special "feature" of the CLV0/CLV1 register set, they must be */
  loop(1) dx0 = CLV1; /* read 4 times in a row to produce a new value. The loop(1) statement  */
  loop(1) dx0 = CLV1; /* is used to make sure that the multiple reads are not optimized away. */
  loop(1) dx0 = CLV1;
  dx0 = dx0 << 10;
  accu1 = (int) dx0;
  clv_phase_err = accu1;

  /* Set the clv_buffer_ok bit to 1 when the desired CLV buffer level   */
  /* (clv_buffer_ok_thres) has been reached. If this causes a change in */
  /* dsp_state an event is send to ARM.                                 */
  /* This test is activated when ARM clears the clv_buffer_ok state bit */
  /* in dsp_state.                                                      */
  if (accu1 >= clv_buffer_ok_thres)
  {
    dsp_state = get_set_clv_buffer_ok(dsp_state);
  }

  if (sw_time == 0)
  {
    c = coeff_clv;
    delay = delay_clv;

    if (disc_mode_int == KICK_MODE)
    {
      DSP_DSPD = spindle_kick;
      delay[4] = delay[5] = 0;
      delay[1] = delay[2] = 0;
      delay[3] = 0;
    }
    else
    {
      if (disc_mode_int == CDV_MODE)
      {
        DSP_DSPD = target_p1T;
        delay[4] = delay[5] = 0;
        delay[1] = delay[2] = 0;
        delay[3] = 0;
      }
      else if ((disc_mode_int == HOLD_MODE) || ((disc_mode_int == CLV_MODE) && (jump_mode || trk_defect)))  /* When controller in CLV mode the hold controller during jump and defect */
      {
        if (DSP_DSPD < 0)
        {
          /* No breaking during short jump or defect. */  /* MR20050106c */
          DSP_DSPD = 0;
        }
        dsp_state = get_clr_ttm_speed_ok(dsp_state);      /* Reset speed_ok */ /* MR20050106b */
      }
      else
      {
        loop(1) dx0 = CLV0; /* Special "feature" of the CLV0/CLV1 register set, they must be */
        loop(1) dx0 = CLV0; /* read 4 times in a row to produce a new value. The loop(1) statement  */
        loop(1) dx0 = CLV0; /* is used to make sure that the multiple reads are not optimized away. */
        loop(1) dx0 = CLV0;

        accu1 = (fraction)((int)((unsigned)dx0 >> 1) - (int)((unsigned)target_p1T >> 1));     /* MR20050523a */
        clv_freq_err = accu1;

        accu0 = accu1 * c[1];
        accu1 = accu0 * c[2] + delay[1] * c[3];
        delay[4] = saturate(accu1);
        accu1 = accu0 * c[4];
        accu0 = accu1 + delay[4];

#if (1 == OPTIMIZED_SHIFT_OUT_PREVENTION) /* MR20060201d */
        /* Prevent shifting out sign-bit for large shifts */
        /* and stop integration when in saturation. */
        dx0 = c[0];
        accu1 = cls(accu0);
        accu1++;
        accu1 = min(accu1, dx0);
        accu1 = accu0 << (int)accu1;
        /$
          jext LabelTTM_HoldInt1
        $/
        delay[6] = delay[4];    /* Integration performed only when shift result is not extended. */
        /$
LabelTTM_HoldInt1:
        $/
        accu1 = saturate(accu1);
        delay[3] = accu1;
#else
        /* Prevent shifting out sign-bit for large shifts */
        dx0 = c[0];
        accu1 = cls(accu0);
        if ((accu1 >= dx0) || (accu1 == 0x0000))
        {
          accu1 = accu0 << (int) dx0;
          delay[6] = delay[4];
        }
        else if (accu0 >= (fraction) 0x0000)
        {
          accu1 = (fraction) 0x7fff;
        }
        else
        {
          accu1 = (fraction) 0x8000;
        }

        delay[3] = accu1;
#endif /* OPTIMIZED_SHIFT_OUT_PREVENTION */

        dx0 = clv_phase_err;
        accu0 = dx0 * c[6];
        accu1 = accu0 * c[7] + delay[2] * c[8];
        delay[5] = saturate(accu1);
        accu1 = accu0 * c[9];
        accu0 = accu1 + delay[5];

#if (1 == OPTIMIZED_SHIFT_OUT_PREVENTION) /* MR20060201d */
        /* Prevent shifting out sign-bit for large shifts */
        /* and stop integration when in saturation. */
        dx0 = c[5];
        accu1 = cls(accu0);
        accu1++;
        accu1 = min(accu1, dx0);
        accu1 = accu0 << (int)accu1;
        /$
          jext LabelTTM_HoldInt2    /* Integration performed only when shift result is not extended. */
        $/
        delay[7] = delay[5];
        /$
LabelTTM_HoldInt2:
        $/
        accu0 = saturate(accu1 + delay[3]);
#else
        /* Prevent shifting out sign-bit for large shifts */
        dx0 = c[5];
        accu1 = cls(accu0);
        if ((accu1 >= dx0) || (accu1 == 0x0000))
        {
          accu1 = accu0 << (int) dx0;
          delay[7] = delay[5];
        }
        else if (accu0 >= (fraction) 0x0000)
        {
          accu1 = (fraction) 0x7fff;
        }
        else
        {
          accu1 = (fraction) 0x8000;
        }

        accu0 = saturate(accu1 + delay[3]);
#endif  /* OPTIMIZED_SHIFT_OUT_PREVENTION */

        dx0 = spdl_limit_min;       /* MR20050523c */
        if (accu0 < dx0)
        {
          accu0 = dx0;
        }
        else
        {
          dx0 = spdl_limit_max;     /* MR20050523c */
          if (accu0 > dx0)
          {
            accu0 = dx0;
          }
          else
          {
            delay[2] = delay[7];
            delay[1] = delay[6];
          }
        }

        DSP_DSPD = accu0;

        /* Generate ttm_speed_ok signal. */
        dsp_state = get_clr_ttm_speed_ok(dsp_state);     /* Reset speed_ok */ /* MR20050106b */
        if (((disc_mode_int == CLV_MODE) && (abs(clv_freq_err) < clv_freq_err_max) && (abs(clv_phase_err) < clv_phase_err_max)) ||
             (disc_mode_int == CDV_MODE))
        {
          dsp_state = get_set_ttm_speed_ok(dsp_state);
        }
      }
    }
    sw_time = clv_ds;
  }   /* MR041215 - END */
  else
  {
    if ((TCR_ON_INT) && (!jump_mode) && (count16 == 0x0B))
    {

#if (1 == ALTERNATIVE_TEOK)
    /**************************************************************************/
    /* Alternative implementation of on-track checking.                       */
    /* ---------------------------------------------------------------------- */
    /* The implementation monitors the track-counter in the RATE block        */
    /* (ntracks). When the reading spot is not (yet) on track the track-      */
    /* counter will count track and ntracks is constantly changing. Also when */
    /* during play, for whatever reason, the reading spot ends up on a        */
    /* neighbopuring track the value of ntracks will change. In this version  */
    /* of on-track checking the state bit tracking_ok in dsp_state is set by  */
    /* ARM and reset by the DSP whenever a change in ntracks is noticed.      */
    /* The state change will cause an event to be send to ARM.                */
    /**************************************************************************/
#if (1 == WORKAROUND_SPIKE_BUG)
      dx0 = DEC9;
      dy0 = DEC9;
      if (dx0 != dy0) {      /* Make sure that DEC9 (ntracks) not read during the decimation filter update of DEC9. */
        dx0 = DEC9;
      }
#else
      dx0 = DEC9;
#endif

      if (ntracks != dx0)
      {
        /* Reset teok when ntracks has changed value. */
        dsp_state = get_clr_tracking_glitch(dsp_state);
      }
      ntracks = dx0;

#else
    /**************************************************************************/
    /* Alternative implementation of on-track checking.                       */
    /* ---------------------------------------------------------------------- */
    /* The state bit tracking_ok is set by ARM and every time the DSP detects */
    /* that the absolute value of the low pass filtered te signal exceeds a   */
    /* certain threshold te_thr, i.e. when the reading spot is not on track,  */
    /* this state bit in dsp_state is reset.                                  */
    /* The state change will cause an event to be send to ARM.                */
    /* The problem with this implementation is that the amplitude/gain of the */
    /* te signal is must lower when the radial tracking actuator is           */
    /* positioned at the edge of the OPU ho