memutil.c

本程序为ST公司开发的源代码

/******************************************************************************/
/*! \file
 *
 *  Project Scope:  CDM M8
 *
 *  Organization:   Philips APM-DS
 *
 *  Version Control:
 *    \source       sources/main/memutil.c
 *    \version      0.1
 *    \author       Bernard Bosnjak
 *    \date         23.05.2006
 *
 *  Target Hardware:    Accordo+ (ARM core)
 *******************************************************************************
 *  \brief        Memory testing and initialization
 *
 *  \par          Change History:
 *
 ***************************************************
 *
 * STM CVS Log:
 *
 * $Log: memutil.c,v $
 * Revision 1.11  2006/11/22 12:50:46  marcucci
 * Safer sdram_init: wait added after Reset Release and Clock Enable
 *
 * Revision 1.10  2006/09/18 09:55:23  belardi
 * Corrected CVS keyword usage
 *
 * Revision 1.9  2006/09/18 09:24:43  belardi
 * Added Log CVS keyword into file header
 *
 *
 ******************************************************************************/

#include "gendef.h"
#include "hwreg.h"
#include "osal.h"
#include "memutil.h"
#include "utility.h"

typedef uint16 datum;

/******************************************************************************/
/* Function:  sdram_init                                                  */
/*                                                                            */
/*! \brief    SDRAM initization
 *  \param
 *  \return
 *  \remark
 */
/******************************************************************************/

void sdram_init(uint32 PATCH_TABLE_ADDRESS)
{
  uint32 i;

  GCR1.field.sdram_sel = 1;

  
  SAB_PCG0.field.sdramc = 1; // Bit 9   0x0200
 
  SAB_PUR0.field.sdramc = 1; // Bit 9   0x0200
 
 
  // BootLoader starts with SDRAM H/W block under reset and with no Clock
  // To understand if the SDRAM has been initialized Bootloader check these 2 bits
  CGC_PCG1.field.sdramc = 1;
  CGC_PUR1.field.sdramc = 1;

  // Initialize and Load Mode Register
  // NOP
  // PRECHARGE
  // AUTO REFRESH
  // NOP
  // AUTO REFRESH
  // NOP
  // LOAD MODE REGISTER
  // NOP
    // ACTIVE
    
  for(i=0; i<50000 ;i++); // Wait  

  SDRAM_CONFIG_HI.all = 0x00; // NOP

  for(i=0; i<10000 ;i++); // Wait

  //SDRAM_MEM_CONFIG.field.refr = 0 ;
  //SDRAM_MEM_CONFIG.field.ben = 1 ;
  //SDRAM_MEM_CONFIG.field.pwrsave = 0 ;
  SDRAM_MEM_CONFIG.all = 0x1100;

  //SDRAM_MBCONFIG.field.sdramcol = 0;
  //SDRAM_MBCONFIG.field.idletime = 1;
  //SDRAM_MBCONFIG.field.setuptime = 1; //bit 5-7
  //SDRAM_MBCONFIG.field.datalat = 2; //bit 8-9
  //SDRAM_MBCONFIG.field.devwid = 1;

  SDRAM_MBCONFIG.all = 0x624;


#ifndef APM_PICKUP
  SDRAM_BANK_SIZE = 128; // DRAM Size 64Mbit 8Mbyte = 128 * 64Kbytes

  SDRAM_CONFIG_LO = 0x400;
  SDRAM_CONFIG_HI.all = 0x00;  // NOP
#else
  SDRAM_BANK_SIZE = 0x1F;
#endif

  SDRAM_CONFIG_LO = 0x400;
  SDRAM_CONFIG_HI.all = 0x05;  // Precharge

  for(i=0; i<10; i++);
  SDRAM_CONFIG_HI.all = 0x03;  // CBR # 1
  for(i=0; i<10; i++);
  SDRAM_CONFIG_HI.all = 0x03;  // CBR # 2
  for(i=0; i<10; i++);
  SDRAM_CONFIG_HI.all = 0x03;  // CBR # 3
  for(i=0; i<10; i++);
  SDRAM_CONFIG_HI.all = 0x03;  // CBR # 4
  for(i=0; i<10; i++);
  SDRAM_CONFIG_HI.all = 0x03;  // CBR # 5
  for(i=0; i<10; i++);
  SDRAM_CONFIG_HI.all = 0x03;  // CBR # 6
  for(i=0; i<10; i++);
  SDRAM_CONFIG_HI.all = 0x03;  // CBR # 7
  for(i=0; i<10; i++);
  SDRAM_CONFIG_HI.all = 0x03;  // CBR # 8

#ifdef APM_PICKUP
  for(i=0; i<10; i++);
  SDRAM_CONFIG_HI.all = 0x03;  // CBR # 9
  for(i=0; i<10; i++);
  SDRAM_CONFIG_HI.all = 0x03;  // CBR # 10
  for(i=0; i<10; i++);
  SDRAM_CONFIG_HI.all = 0x03;  // CBR # 11
  for(i=0; i<10; i++);
  SDRAM_CONFIG_HI.all = 0x03;  // CBR # 12
  for(i=0; i<10; i++);
  SDRAM_CONFIG_HI.all = 0x03;  // CBR # 13
  for(i=0; i<10; i++);
  SDRAM_CONFIG_HI.all = 0x03;  // CBR # 14
  for(i=0; i<10; i++);
  SDRAM_CONFIG_HI.all = 0x03;  // CBR # 15
#endif

  SDRAM_CONFIG_LO = 0x0020;    // SDRAM Mode Register
  SDRAM_CONFIG_HI.all = 0x7;   // MRS

#ifndef APM_PICKUP
  SDRAM_MEM_CONFIG.all = 0x1130;
#else
  SDRAM_MEM_CONFIG.all = 0x1142;
#endif

 for(i=0; i<10000 ;i++); // Wait
}

#ifdef APM_PICKUP // [RB] commented out to reduce ROM space
datum memTestDataBus(volatile register datum *address)
{
  register datum pattern;

  /*
   * Perform a walking 1's test at the given address.
   */
  for (pattern = 1; pattern != 0; pattern <<= 1)
  {
    /*
     * Write the test pattern.
     */
    *address = pattern;

    /*
     * Read it back (immediately is okay for this test).
     */
    if (*address != pattern)
    {
      return (pattern);
    }
  }

  return (0);
}

#define pattern     (datum)0xAAAAAAAA
#define antipattern (datum)0x55555555
datum * memTestAddressBus(volatile  register datum *baseAddress, register uint32 nBytes)
{
  const uint32 register addressMask = (nBytes/sizeof(datum) - 1);
  uint32 register offset;
  uint32 register testOffset;

  /*
   * Write the default pattern at each of the power-of-two offsets.
   */
  for (offset = sizeof(datum); (offset & addressMask) != 0; offset <<= 1)
  {
    baseAddress[offset] = pattern;
  }

  /*
   * Check for address bits stuck high.
   */
  testOffset = 0;
  baseAddress[testOffset] = antipattern;
  for (offset = sizeof(datum); (offset & addressMask) != 0; offset <<= 1)
  {
    if (baseAddress[offset] != pattern)
    {
      return ((datum *)&baseAddress[offset]);
    }
  }

  baseAddress[testOffset] = pattern;
  /*
   * Check for address bits stuck low or shorted.
   */
  for (testOffset = sizeof(datum); (testOffset & addressMask) != 0; testOffset <<= 1)
  {
    baseAddress[testOffset] = antipattern;

    for (offset = sizeof(datum); (offset & addressMask) != 0; offset <<= 1)
    {
      if ((baseAddress[offset] != pattern) && (offset != testOffset))
      {
        return ((datum *)&baseAddress[testOffset]);
      }
    }

    baseAddress[testOffset] = pattern;
  }

  return (NULL);
}
#undef pattern
#undef antipattern

datum * memTestDevice(volatile register datum *baseAddress, register uint32 nBytes)
{
  register uint32 offset;
  const  register uint32 nWords = nBytes / sizeof(datum);

  datum pattern;
  datum antipattern;

  /*
   * Fill memory with a known pattern.
   */
  for (pattern = 1, offset = 0; offset < nWords; pattern++, offset++)
  {
    baseAddress[offset] = pattern;
  }

  /*
   * Check each location and invert it for the second pass.
   */
  for (pattern = 1, offset = 0; offset < nWords; pattern++, offset++)
  {
    if (baseAddress[offset] != pattern)
    {
      return ((datum *)&baseAddress[offset]);
    }
    antipattern = ~pattern;
    baseAddress[offset] = antipattern;
  }

  /*
   * Check each location for the inverted pattern and zero it.
   */
  for (pattern = 1, offset = 0; offset < nWords; pattern++, offset++)
  {
    antipattern = ~pattern;
    if (baseAddress[offset] != antipattern)
    {
      return ((datum *)&baseAddress[offset]);
    }

    baseAddress[offset] = 0;
  }

  return (NULL);
}

#define SDRAM_BASE_ADDRESS  0x80000000
#define SDRAM_NUM_BYTES     0x00200000
uint8 SDRAM_Test(void)
{
  if (memTestDataBus((volatile datum *)SDRAM_BASE_ADDRESS) != 0)
  {
    return 1;
  }
  if (memTestAddressBus((volatile datum *)SDRAM_BASE_ADDRESS, SDRAM_NUM_BYTES) != NULL)
  {
    return 2;
  }
  if (memTestDevice((volatile datum *)SDRAM_BASE_ADDRESS, SDRAM_NUM_BYTES) != NULL)
  {
    return 3;
  }
  return 0;
}

__asm set_stack(int addr)
{
  add sp,r0,#0
  bx lr
}

#define RAMA_BASE_ADDRESS  0x40000000
#define RAMA_NUM_BYTES     0x18000
#define RAMB_BASE_ADDRESS  0x60000000
#define RAMB_NUM_BYTES     0x8000
void RAM_Test(void)
{
  (void)EIC_vEicGlobalDis();
  configure_gpio(PORT_B, GPIO_4, GPIO_OUT_PP);    // TX0
  configure_gpio(PORT_B, GPIO_5, GPIO_OUT_PP);    // RX0
  set_gpio(PORT_B, GPIO_4, 0);
  set_gpio(PORT_B, GPIO_5, 0);

  set_stack(RAMB_BASE_ADDRESS + 0x100);
  if ((memTestDataBus((volatile datum *)RAMA_BASE_ADDRESS) != 0)
   || (memTestAddressBus((volatile datum *)RAMA_BASE_ADDRESS, RAMA_NUM_BYTES) != NULL)
   || (memTestDevice((volatile datum *)RAMA_BASE_ADDRESS, RAMA_NUM_BYTES) != NULL))
  {
    /* error */
    while (1)
    {
      set_gpio(PORT_B, GPIO_4, 1);
      set_gpio(PORT_B, GPIO_4, 0);
    }
  }
   
  set_stack(RAMA_BASE_ADDRESS + 0x100);
  if ((memTestDataBus((volatile datum *)RAMB_BASE_ADDRESS) != 0)
   || (memTestAddressBus((volatile datum *)RAMB_BASE_ADDRESS, RAMB_NUM_BYTES) != NULL)
   || (memTestDevice((volatile datum *)RAMB_BASE_ADDRESS, RAMB_NUM_BYTES) != NULL))
  {
    /* error: do nothing */
    while (1)
    {
      set_gpio(PORT_B, GPIO_4, 1);
      set_gpio(PORT_B, GPIO_4, 0);
    }
  }

  while (1)
  {
    set_gpio(PORT_B, GPIO_5, 1);
    set_gpio(PORT_B, GPIO_5, 0);
  }
}
#endif