hwinit.c

本程序为ST公司开发的源代码

 *  \return   void
 *  \remark
 */
/******************************************************************************/
void rccu_init(void)
{
  uint32 lockbit;

  RCCU_PLLCONF_UNION rccu_pllconf;

  switch_off_pll();

  rccu_pllconf.field.p = RUN_MODE;
  rccu_pllconf.field.pllbyp = 1;
  rccu_pllconf.field.plloff = 1;
  rccu_pllconf.field.autobyp_en = 0;
  RCCU_SYSPROT.field.reg_prot = 1;        // Enable RCCU_PLLCONF & RCCU_CLKCTL writing.
  RCCU_PLLCONF.all = rccu_pllconf.all;    // Set Division Factor.

  rccu_pllconf.field.p = RUN_MODE;
  rccu_pllconf.field.pllbyp = 1;
  rccu_pllconf.field.plloff = 0;
  rccu_pllconf.field.autobyp_en = 0;

  RCCU_SYSPROT.field.reg_prot = 1;        // Enable RCCU_PLLCONF & RCCU_CLKCTL writing.
  RCCU_PLLCONF.all = rccu_pllconf.all;    // Switch on PLL.

  while (1)
  {
    lockbit = RCCU_PLLCONF.field.lock;
    if (lockbit)
    {
      break;
    }
  }

  rccu_pllconf.field.p = RUN_MODE;
  rccu_pllconf.field.pllbyp = 0;
  rccu_pllconf.field.plloff = 0;
  rccu_pllconf.field.autobyp_en = 0;

  RCCU_SYSPROT.field.reg_prot = 1;      // Enable RCCU_PLLCONF & RCCU_CLKCTL writing.
  RCCU_PLLCONF.all = rccu_pllconf.all;  // PLL Enable

  enable_clock();
}


/******************************************************************************/
/* Function:  switch_off_pll                                                  */
/*                                                                            */
/*! \brief    Switch off the PLL
 *  \param    void
 *  \return   void
 *  \remark
 */
/******************************************************************************/
void switch_off_pll(void)
{
  uint32 lockbit;

  RCCU_SYSPROT.field.reg_prot = 1;         // Enable RCCU_PLLCONF & RCCU_CLKCTL writing.
  RCCU_PLLCONF.field.pllbyp = 1;

  while (1)
  {
    if (RCCU_CLKFLAG.field.pllbyp_f)
    {
      break;
    }
  }

  RCCU_SYSPROT.field.reg_prot = 1;         // Enable RCCU_PLLCONF & RCCU_CLKCTL writing.
  RCCU_PLLCONF.field.plloff = 1;

  while (1)
  {
    lockbit = RCCU_PLLCONF.field.lock;
    if (!lockbit)
    {
      break;
    }
  }
}


/******************************************************************************/
/* Function:  enable_clock                                                    */
/*                                                                            */
/*! \brief    Enable the clock
 *  \param    void
 *  \return   void
 *  \remark
 */
/******************************************************************************/
void enable_clock(void)
{
  RCCU_CLKCTL_UNION rccu_clkctl;

  rccu_clkctl = RCCU_CLKCTL;

  rccu_clkctl.field.en_clk_13 = 1;
  rccu_clkctl.field.en_clk_6 = 1;
  rccu_clkctl.field.en_clk_44 = 1;
  rccu_clkctl.field.en_clk_2 = 1;
  rccu_clkctl.field.en_clk_33 = 1;
  rccu_clkctl.field.en_clk_16 = 1;

  RCCU_SYSPROT.field.reg_prot = 1;      // Enable RCCU_PLLCONF & RCCU_CLKCTL writing.
  RCCU_CLKCTL.all = rccu_clkctl.all;
}




/******************************************************************************/
/* Function:  src_init                                                        */
/*                                                                            */
/*! \brief    Initialize the SampleRateConverter hardware
 *  \param    void
 *  \return   void
 *  \remark
 */
/******************************************************************************/
void src_init(void)
{
  CIF_CONF.field.src = 1;

  SRC_CS.field.en = 0;

  SRC_CS.field.ielock = 0; // Disable LOCK Interrupt
  SRC_CS.field.mute = 0;
  SRC_CS.field.dither_en = 0;

  SRC_CS.field.lpf_sel = SRC_UPX4; // 3 -> 8-16Khz
  SRC_DIV = SRC_8K;

  //OSAL_isr_install(OSAL_ISR_SRC_FULL, 0x0f, src_data_full_irq);
  //OSAL_isr_install(OSAL_ISR_SRC_EMPTY, 0x0f, src_data_empty_irq);
  OSAL_isr_install(OSAL_ISR_SRC_ERROR, 0x0f, src_error_isr_irq);

  //MM_SRC
  DMA_CTRL0.field.enable = 0;
  dma_ch0_fiq = 0;

  SetDMAChannel(DMA_CH0, SRC_DRE_CH);

  //OSAL_isr_install(OSAL_ISR_DMA, 0x0f, dma_ch2_isr_irq);  //MM_SRC
  OSAL_isr_install(OSAL_ISR_DMA0, 0x0f, dma_ch0_isr_irq); //MM_SRC
  EIC_ICR.field.fiq_en = 1;
  EIC_FIR.field.dma0_fiq_en = 1;

  SetUpDMA(DMA_CH0,
           (uint32 *) NULL,                    // Source Address
           (uint32 *)&SRC_DIF,                 // Destination Address
           DMA_WORD_SIZE_IS_HALF_WORD,         // Source Word Size
           DMA_WORD_SIZE_IS_HALF_WORD,         // Destination Word Size
           0,                                  // Number of Words
           DMA_BURST_IS_4_WORD,                // Burst Size
           DMA_INCREMENT,                      // Source Inc
           DMA_NO_INCREMENT,                   // Peripheral Inc
           DMA_PERIPHERAL_IS_THE_DESTINATION,  // Peripheral is Destination
           0);                                 // Mem 2 Mem Enable

  DMA_MASK.field.sim0 = 1;
  DMA_MASK.field.sem0 = 1;

  DMA_CLR.field.sic0 = 1;
  DMA_CLR.field.sec0 = 1;

  SRC_CS.field.ifsm_rst = 1; // Reset the Finite State Machine for SRC_DIF reg
  SRC_CS.field.ofsm_rst = 1; // Reset the Finite State Machine for SRC_DOF reg

  SRC_CS.field.dedre = 1; // Enable DMA Empty
  SRC_CS.field.dedrf = 0; // Disable DMA Full
  SRC_CS.field.ieufl = 0; // [MM] Enable SRC underflow interrupt
                          //      otherwise on first underflow the SRC hangs
                          //      because nobody clears the UFL bit
                          //      This is one of the causes of the random decoder freezes
                          // [MM] Disabled since it is not raised by the hw (HW BUG?)
}

/******************************************************************************/
/* Function: enable_DMA0                                                      */
/*                                                                            */
/*! \brief
 *  \param    void
 *  \return   void
 *  \remark
 */
/******************************************************************************/
void enable_DMA0(void)
{
  dma_ch0_fiq = 1;
  DMA_CTRL0.field.enable = 1;
}

/******************************************************************************/
/* Function: enable_SRC                                                       */
/*                                                                            */
/*! \brief
 *  \param    void
 *  \return   void
 *  \remark
 */
/******************************************************************************/
#if 0 // [RB] unused
void enable_SRC(void)
{
 #if (SRC_MUTE == 1)      //[MM] 11/08/06
  SRC_CS.field.mute = 0;  //[MM] 11/08/06
 #endif                   //[MM] 11/08/06
  SRC_CS.field.en = 1;
}
#endif

/******************************************************************************/
/* Function: set_DMA0                                                         */
/*                                                                            */
/*! \brief
 *  \param    void
 *  \return   void
 *  \remark
 */
/******************************************************************************/
void set_DMA0(uint32 *src, uint32 count)
{
  DMA_SOURCE_HI0 = ((uint32)(src) >> 16);
  DMA_SOURCE_LO0 = ((uint32)(src) & 0xFFFF);
  DMA_MAX0 = count;
}

/******************************************************************************/
/* Function: SRCSetFrequency                                                  */
/*                                                                            */
/*! \brief
 *  \param    freq
 *  \return   void
 *  \remark
 */
/******************************************************************************/
void SRCSetFrequency(eDecoderSampleRate freq)
{
  SRC_CS.field.en = 0;

  SRC_CS.field.ifsm_rst = 1;  // Reset the Finite State Machine for SRC_DIF reg
  SRC_CS.field.ofsm_rst = 1;  // Reset the Finite State Machine for SRC_DOF reg

  switch (freq)
  {
  case (kDecoderSampleRate_8000Hz):
    SRC_DIV = SRC_8K;
    SRC_CS.field.lpf_sel = SRC_UPX4;  // 3 -> 8-16Khz
    break;
  case (kDecoderSampleRate_11025Hz):
    SRC_DIV = SRC_11K;
    SRC_CS.field.lpf_sel = SRC_UPX4;  // 3 -> 8-16Khz
    break;
  case (kDecoderSampleRate_12000Hz):
    SRC_DIV = SRC_12K;
    SRC_CS.field.lpf_sel = SRC_UPX4;  // 3 -> 8-16Khz
    break;
  case (kDecoderSampleRate_16000Hz):
    SRC_DIV = SRC_16K;
    SRC_CS.field.lpf_sel = SRC_UPX2;  // 16-32Khz
    break;
  case (kDecoderSampleRate_22050Hz):
    SRC_DIV = SRC_22K;
    SRC_CS.field.lpf_sel = SRC_UPX2;  // 16-32Khz
    break;
  case (kDecoderSampleRate_24000Hz):
    SRC_DIV = SRC_24K;
    SRC_CS.field.lpf_sel = SRC_UPX2;  // 16-32Khz
    break;
  case (kDecoderSampleRate_32000Hz):
    SRC_DIV = SRC_32K;
    SRC_CS.field.lpf_sel = SRC_DIRECT;  // 32-44.1Khz
    break;
  case (kDecoderSampleRate_44100Hz):
    SRC_DIV = SRC_44K;
    SRC_CS.field.lpf_sel = SRC_DIRECT;  // 32-44.1Khz
    break;
  case (kDecoderSampleRate_48000Hz):
    SRC_DIV = SRC_48K;
    SRC_CS.field.lpf_sel = SRC_DOWN;    // 44.1-48Khz
    break;
  default:
    // use 44100 for default
    SRC_DIV = SRC_44K;
    SRC_CS.field.lpf_sel = SRC_DIRECT;  // 32-44.1Khz
    break;
  }
#if (SRC_MUTE == 1)       //[MM] 11/08/06
  SRC_CS.field.mute = 0;  //[MM] 11/08/06
#endif                    //[MM] 11/08/06
  SRC_CS.field.en = 1;
}


/******************************************************************************/
/* Function: src_stop                                                         */
/*                                                                            */
/*! \brief
 *  \param
 *  \return
 *  \remark
 */
/******************************************************************************/

void src_stop(void)
{
 #if (SRC_MUTE == 1)      //[MM] 11/08/06
  SRC_CS.field.mute = 1;  //[MM] 11/08/06
 #endif                   //[MM] 11/08/06
  SRC_CS.field.en = 0;

  SRC_CS.field.dedre = 0; // Enable DMA Empty
}

/******************************************************************************/
/* Function: src_restart                                                      */
/*                                                                            */
/*! \brief
 *  \param
 *  \return
 *  \remark
 */
/******************************************************************************/

void src_restart(void)
{
  SRC_CS.field.ifsm_rst = 1; // Reset the Finite State Machine for SRC_DIF reg
  SRC_CS.field.ofsm_rst = 1; // Reset the Finite State Machine for SRC_DOF reg

  SRC_CS.field.dedre = 1; // Enable DMA Empty
  SRC_CS.field.dedrf = 0; // Disable DMA Full
  SRC_CS.field.ieufl = 0; // Underflow

  SRC_CS.field.mute = 0;
  SRC_CS.field.en = 1;
}

/******************************************************************************/
/* Function:  misc_ap_isr                                                     */
/*                                                                            */
/*! \brief    misc AP interrupt handler
 *  \param    void
 *  \return   void
 *  \remark
 */
/******************************************************************************/

void misc_ap_isr(void)
{
    //STTODO what is this used for? do we need event?
  if (OIF_SP_CFG.field.int_frame_complete)
    {
    OIF_SP_CFG.field.int_frame_complete = 1;  
    //controller_update_status(CONTROLLER_SWITCH_CH_EVENT);

    OSAL_wake_thread(OSAL_THREAD_ControllerTask);
    }
     }
  	
/******************************************************************************/
/* Function: enable_CIF                                                       */
/*                                                                            */
/*! \brief
 *  \param    void
 *  \return   void
 *  \remark
 */
/******************************************************************************/

void enable_CIF(void)
{
  //CIF_CONF.field.rd_en = 0;
  //CIF_CONF.field.wr_fifo_rst = 1;
  CIF_CONF.field.wr_en = 1;
  //CIF_CONF.field.rd_en = 1;
}

/******************************************************************************/
/* Function: enable_DeEmphasis                                                       */
/*                                                                            */
/*! \brief
 *  \param    void
 *  \return   void
 *  \remark
 */
/******************************************************************************/

void enable_DeEmphasis(void)
{
  OIF_AP_CONTROL_PART_2.field.enable_deemphasis  = 1;
}

/******************************************************************************/
/* Function: disable_DeEmphasis                                                       */
/*                                                                            */
/*! \brief
 *  \param    void
 *  \return   void
 *  \remark
 */
/******************************************************************************/

void disable_DeEmphasis(void)
{
  OIF_AP_CONTROL_PART_2.field.enable_deemphasis = 0;
}