hwinit.c

本程序为ST公司开发的源代码

/**************************************************
 *
 * hwinit.c
 *
 * CVS ID:   $Id: hwinit.c,v 1.41 2007/10/25 10:13:44 marcucci Exp $
 * Author:   Maurizio Marcucci [MM] - STM
 * Date:     $Date: 2007/10/25 10:13:44 $
 * Revision: $Revision: 1.41 $
 *
 * Description:
 *
 *   Hardware initializations for the Accordo+ chip.
 *
 ***************************************************
 *
 * COPYRIGHT (C) ST Microelectronics  2005
 *            All Rights Reserved
 *
 ***************************************************
 *
 * STM CVS Log:
 *
 * $Log: hwinit.c,v $
 * Revision 1.41  2007/10/25 10:13:44  marcucci
 * Set PORTB GPIO 2 & GPIO 3 as inputt to  allow to configure them as
 * SCL & SDA lines only after complete I2C Hardware initialization
 *
 * Revision 1.40  2007/10/22 08:30:17  marcucci
 * More robust waiting for DMA complete
 *
 * Revision 1.39  2007/10/12 13:22:02  marcucci
 * GPA5 and GPA6  pins set as input after reset
 *
 * Revision 1.38  2007/08/14 15:28:13  dellorto
 * multiple mechanisms
 *
 * Revision 1.37  2007/08/08 08:14:24  longauer
 * HIGH-Z feature support - GPIO B4 set as output
 *
 * Revision 1.36  2007/06/28 20:53:52  longauer
 * 1.Usb restructuralization in order to supports more LUNs and interface preparation
 *  for iAP; 2.PHY emulation moved; 3.compilation works with IPOD_PASSTHROUGH==0; 4.
 *  usb patching init moved from main.c
 *
 * Revision 1.35  2006/11/25 08:14:49  belardi
 * Ununsed function removal to free code space
 *
 * Revision 1.34  2006/09/18 09:55:23  belardi
 * Corrected CVS keyword usage
 *
 * Revision 1.33  2006/09/18 09:24:43  belardi
 * Added Log CVS keyword into file header
 *
 *
 ***************************************************/

#include "gendef.h"
#include "hwreg.h"

#include "rccu_run.h" // for RUN_MODE
#include "hwinit.h"
#include "utility.h"
#include "isrchdl.h"
#include "controller.h"
#include "bkdhdl.h"

// OS20
#include "osal.h"

#define SRC_8K   (S_APB_CLK / 8000)
#define SRC_11K  (S_APB_CLK / 11025)
#define SRC_12K  (S_APB_CLK / 12000)
#define SRC_16K  (S_APB_CLK / 16000)
#define SRC_22K  (S_APB_CLK / 22050)
#define SRC_24K  (S_APB_CLK / 24000)
#define SRC_32K  (S_APB_CLK / 32000)
#define SRC_44K  (S_APB_CLK / 44100)
#define SRC_48K  (S_APB_CLK / 48000)

#define SRC_DIRECT   0x00 // Input Sample rate 32K-44.1K
#define SRC_DOWN     0x01 // Input Sample rate 44.1K-48K
#define SRC_UPX2     0x02 // input Sample rate 16K-32K
#define SRC_UPX4     0x03 // input Sample rate 8K-16K

extern void dma_ch0_isr_fiq(void); // connected to FIQ (outside OS)
extern void dma_ch0_isr_irq(void); // connected to IRQ
void rccu_init(void);
void switch_off_pll(void);
void enable_clock(void);
void REENT_INT_IRQ(void);

extern volatile uint8  dma_ch0_fiq;
/******************************************************************************/
/* Function:  hw_init                                                         */
/*                                                                            */
/*! \brief    Turn on various peripherals, configure GPIO
 *  \param    void
 *  \return   void
 *  \remark
 */
/******************************************************************************/
void hw_init(void)
{
  rccu_init();

  // Switch-on  SYNC_APB Peripherals
  {
    SAB_PER_BIT_UNION sab_pcg0;

    sab_pcg0.all = 0;
    sab_pcg0.field.bridge = 1; // Bit 0   0x0001
    sab_pcg0.field.wui = 1;    // Bit 1   0x0002
    sab_pcg0.field.dmac = 1;   // Bit 2   0x0004
    sab_pcg0.field.rccu = 1;   // Bit 3   0x0008
    sab_pcg0.field.bspi = 1;   // Bit 4   0x0010
    sab_pcg0.field.uart0 = 1;  // Bit 5   0x0020
    sab_pcg0.field.uart1 = 1;  // Bit 6   0x0040
    sab_pcg0.field.eft0 = 1;   // Bit 7   0x0080
    sab_pcg0.field.eft1 = 1;   // Bit 8   0x0100
    sab_pcg0.field.sdramc = 1; // Bit 9   0x0200
    sab_pcg0.field.gcr = 1;    // Bit 10  0x0400
    sab_pcg0.field.gpioa = 1;  // Bit 11  0x0800
    sab_pcg0.field.gpiob = 1;  // Bit 12  0x1000
    sab_pcg0.field.i2c = 1;    // Bit 13  0x2000
#if (0 != HAVE_SDC)
    sab_pcg0.field.bspi1 = 1;
#endif /* HAVE_SDC */

    SAB_PCG0.all = sab_pcg0.all;
  }
  {
    SAB_PER_BIT_UNION sab_pur0;

    sab_pur0.all = 0;
    sab_pur0.field.bridge = 1; // Bit 0   0x0001
    sab_pur0.field.wui = 1;    // Bit 1   0x0002
    sab_pur0.field.dmac = 1;   // Bit 2   0x0004
    sab_pur0.field.rccu = 1;   // Bit 3   0x0008
    sab_pur0.field.bspi = 1;   // Bit 4   0x0010
    sab_pur0.field.uart0 = 1;  // Bit 5   0x0020
    sab_pur0.field.uart1 = 1;  // Bit 6   0x0040
    sab_pur0.field.eft0 = 1;   // Bit 7   0x0080
    sab_pur0.field.eft1 = 1;   // Bit 8   0x0100
    sab_pur0.field.sdramc = 1; // Bit 9   0x0200
    sab_pur0.field.gcr = 1;    // Bit 10  0x0400
    sab_pur0.field.gpioa = 1;  // Bit 11  0x0800
    sab_pur0.field.gpiob = 1;  // Bit 12  0x1000
    sab_pur0.field.i2c = 1;    // Bit 13  0x2000
#if (0 != HAVE_SDC)
    sab_pur0.field.bspi1 = 1;
#endif /* HAVE_SDC */

    SAB_PUR0.all = sab_pur0.all;
  }

  SAB_EMPCG0.field.bspi = 0;

  // Switch-on  ASYNC APB Peripherals
  {
    AAB_PER_BIT_UNION aab_pcg0;

    aab_pcg0.all = 0;
    aab_pcg0.field.bridge = 1;    // Bit 0
    aab_pcg0.field.wdg = 0;       // Bit 1 DISABLED BY OS20 FROM MAURIZIO's CODE
    aab_pcg0.field.dsp = 1;       // Bit 2
    aab_pcg0.field.dec = 1;       // Bit 3
    aab_pcg0.field.circ_clv = 1;  // Bit 4
    aab_pcg0.field.afe = 1;       // Bit 5
    aab_pcg0.field.acq = 1;       // Bit 6
    aab_pcg0.field.oif = 1;       // Bit 7
    aab_pcg0.field.block_dec = 0; // Bit 8

    AAB_PCG0.all = aab_pcg0.all;
    AAB_PCG0.field.block_dec = 1; // Bit 8  // FB this bit is 1 at reset, so we want to cycle
  }
  {
    AAB_PER_BIT_UNION aab_pur0;

    aab_pur0.all = 0;
    aab_pur0.field.bridge = 1;    // Bit 0
    aab_pur0.field.wdg = 1;       // Bit 1
    aab_pur0.field.dsp = 1;       // Bit 2
    aab_pur0.field.dec = 1;       // Bit 3
    aab_pur0.field.circ_clv = 1;  // Bit 4
    aab_pur0.field.afe = 1;       // Bit 5
    aab_pur0.field.acq = 1;       // Bit 6
    aab_pur0.field.oif = 1;       // Bit 7
    aab_pur0.field.block_dec = 0; // Bit 8

    AAB_PUR0.all = aab_pur0.all;
    AAB_PUR0.field.block_dec = 1; // Bit 8  // FB this bit is 1 at reset, so we want to cycle
  }
  {
    CGC_PCG1_UNION cgc_pcg1;

    cgc_pcg1.all = 0;
    // Switch-on  SYNC AHB Peripherals
    cgc_pcg1.field.eic = 1;
    cgc_pcg1.field.dmac = 1;
    cgc_pcg1.field.sdramc = 1;
    cgc_pcg1.field.exp_ram = 1;
    cgc_pcg1.field.ch_itf = 1;
    cgc_pcg1.field.src = 1;
    cgc_pcg1.field.usb = HAVE_USB;
    cgc_pcg1.field.input_port = 1;

    CGC_PCG1.all = cgc_pcg1.all;
  }
  {
    CGC_PUR1_UNION cgc_pur1;

    cgc_pur1.all = 0;
    cgc_pur1.field.eic = 1;
    cgc_pur1.field.dmac = 1;
    cgc_pur1.field.sdramc = 1;
    cgc_pur1.field.exp_ram = 1;
    cgc_pur1.field.ch_itf = 1;
    cgc_pur1.field.src = 1;
    cgc_pur1.field.usb = HAVE_USB;
    cgc_pur1.field.input_port = 1;

    CGC_PUR1.all = cgc_pur1.all;
  }

#ifdef APM_PICKUP
#if (M8_SAMPLE_VER >= M8VER_A)
  // configure GPIOs
  configure_gpio(PORT_A, GPIO_0, GPIO_OUT_PP); // SEL_I2S/SP-DIF
  configure_gpio(PORT_A, GPIO_1, GPIO_IN);
  configure_gpio(PORT_A, GPIO_2, GPIO_IN);     // SW_INSERT
  configure_gpio(PORT_A, GPIO_3, GPIO_IN);     // SW_EJECT
  configure_gpio(PORT_A, GPIO_4, GPIO_IN);     // SW_STOP
  configure_gpio(PORT_A, GPIO_5, GPIO_AF_PP);  // MON0
  configure_gpio(PORT_A, GPIO_6, GPIO_AF_PP);  // MON1
  configure_gpio(PORT_A, GPIO_7, GPIO_AF_PP);  // MON2
  configure_gpio(PORT_A, GPIO_8, GPIO_IN);
  configure_gpio(PORT_A, GPIO_9, GPIO_OUT_PP);     // LSPEED
  configure_gpio(PORT_A, GPIO_10, GPIO_OUT_PP);    // CTL1
  configure_gpio(PORT_A, GPIO_11, GPIO_OUT_PP);    // CTL2
  configure_gpio(PORT_A, GPIO_12, GPIO_OUT_PP);    // CTL3
  configure_gpio(PORT_A, GPIO_13, GPIO_IN);        // HW_EJECT

  

  configure_gpio(PORT_B, GPIO_0, GPIO_AF_PP);    // SFLASH_SS
  configure_gpio(PORT_B, GPIO_1, GPIO_OUT_OD);   // CRQ
  configure_gpio(PORT_B, GPIO_2, GPIO_AF_PP);   // SCL
  configure_gpio(PORT_B, GPIO_3, GPIO_AF_PP);   // SDA
  configure_gpio(PORT_B, GPIO_4, GPIO_AF_PP);    // TX0
  configure_gpio(PORT_B, GPIO_5, GPIO_IN);       // RX0
  configure_gpio(PORT_B, GPIO_6, GPIO_AF_PP);    // TX1
  configure_gpio(PORT_B, GPIO_7, GPIO_IN);       // RX1
  configure_gpio(PORT_B, GPIO_8, GPIO_AF_PP);    // EF
  configure_gpio(PORT_B, GPIO_9, GPIO_IN);
  configure_gpio(PORT_B, GPIO_10, GPIO_AF_PP);   // SFLAS_RW
  configure_gpio(PORT_B, GPIO_11, GPIO_AF_PP);   // HOME_SW
  configure_gpio(PORT_B, GPIO_12, GPIO_AF_PP);
  configure_gpio(PORT_B, GPIO_13, GPIO_AF_PP);
  configure_gpio(PORT_B, GPIO_14, GPIO_AF_PP);
  configure_gpio(PORT_B, GPIO_15, GPIO_AF_PP);
#else
  // configure GPIOs
  configure_gpio(PORT_A, GPIO_0, GPIO_OUT_PP);
  configure_gpio(PORT_A, GPIO_1, GPIO_OUT_PP);
  configure_gpio(PORT_A, GPIO_2, GPIO_OUT_PP);
  configure_gpio(PORT_A, GPIO_3, GPIO_IN);
  configure_gpio(PORT_A, GPIO_4, GPIO_IN);
  configure_gpio(PORT_A, GPIO_5, GPIO_AF_PP);
  configure_gpio(PORT_A, GPIO_6, GPIO_AF_PP);
  configure_gpio(PORT_A, GPIO_7, GPIO_OUT_PP);
  configure_gpio(PORT_A, GPIO_8, GPIO_IN);

  configure_gpio(PORT_B, GPIO_0, GPIO_OUT_PP);
  configure_gpio(PORT_B, GPIO_1, GPIO_OUT_OD); // use GPIO_OUT_OD for I2C CRQ
  configure_gpio(PORT_B, GPIO_2, GPIO_AF_PP); // use GPIO_AF_PP for I2C SCL
  configure_gpio(PORT_B, GPIO_3, GPIO_AF_PP); // use GPIO_AF_PP for I2C SDA
  configure_gpio(PORT_B, GPIO_4, GPIO_AF_PP);
  configure_gpio(PORT_B, GPIO_5, GPIO_IN);
  configure_gpio(PORT_B, GPIO_6, GPIO_AF_PP);
  configure_gpio(PORT_B, GPIO_7, GPIO_IN);
  configure_gpio(PORT_B, GPIO_8, GPIO_OUT_PP);
#endif

#else /* APM_PICKUP */

  // configure GPIOs
  configure_gpio(PORT_A, GPIO_0, GPIO_OUT_PP);   // DRIVE_CTL
  configure_gpio(PORT_A, GPIO_1, GPIO_OUT_PP);   // LD_FWD
  configure_gpio(PORT_A, GPIO_2, GPIO_OUT_PP);   // LD_REV
  configure_gpio(PORT_A, GPIO_3, GPIO_IN);       // CHUCK_SW
  configure_gpio(PORT_A, GPIO_4, GPIO_IN);       // LOAD_SW
#if (DEBUG_SERVO_SUPPORT == 1)
  configure_gpio(PORT_A, GPIO_5, GPIO_AF_PP);    // MON0
  configure_gpio(PORT_A, GPIO_6, GPIO_AF_PP);    // MON1
  configure_gpio(PORT_A, GPIO_7, GPIO_AF_PP);    // MON2
#else
  configure_gpio(PORT_A, GPIO_5, GPIO_IN);    
  configure_gpio(PORT_A, GPIO_6, GPIO_IN);    
  configure_gpio(PORT_A, GPIO_7, GPIO_IN);       // HW_EJECT  
#endif
  configure_gpio(PORT_A, GPIO_8, GPIO_IN);       // INNER_SW
#ifdef TQFP
  configure_gpio(PORT_A, GPIO_11, GPIO_IN);
#endif
  configure_gpio(PORT_B, GPIO_0, GPIO_OUT_PP);
  configure_gpio(PORT_B, GPIO_1, GPIO_OUT_OD); // use GPIO_OUT_OD for I2C CRQ
  configure_gpio(PORT_B, GPIO_2, GPIO_IN); // use GPIO_AF_PP for I2C SCL
  configure_gpio(PORT_B, GPIO_3, GPIO_IN); // use GPIO_AF_PP for I2C SDA
  configure_gpio(PORT_B, GPIO_4, GPIO_OUT_PP);	// Vbus control or for debugging	//[LL]
  configure_gpio(PORT_B, GPIO_5, GPIO_IN);       // EJECT_12/8_SW
#if (0 != HAVE_USB)
  configure_gpio(PORT_B, GPIO_6, GPIO_IN);    // USB - USBDM
  configure_gpio(PORT_B, GPIO_7, GPIO_IN);    // USB - USBDP
  configure_gpio(PORT_B, GPIO_8, GPIO_IN);    // USB - USBCK
#else
  configure_gpio(PORT_B, GPIO_6, GPIO_AF_PP);
  configure_gpio(PORT_B, GPIO_7, GPIO_IN);
  configure_gpio(PORT_B, GPIO_8, GPIO_IN);

  set_gpio(PORT_A, GPIO_7, 1);  // enable 48MHz clock
#endif

#if (HAVE_MULTI_MECHANISM == 1)
  configure_gpio(PORT_B, GPIO_9, GPIO_IN);        // SW0_MM
  configure_gpio(PORT_B, GPIO_10, GPIO_IN);       // SW1_MM
  configure_gpio(PORT_B, GPIO_11, GPIO_IN);       // SW2_MM
#elif (DEBUG_SERVO_SUPPORT == 1)
  configure_gpio(PORT_B, GPIO_9, GPIO_OUT_PP);    // TEST0
  configure_gpio(PORT_B, GPIO_10, GPIO_OUT_PP);   // TEST1
  configure_gpio(PORT_B, GPIO_11, GPIO_OUT_PP);   // TEST2
#endif

#if (0 != HAVE_SDC)
  configure_gpio(PORT_B, GPIO_12, GPIO_OUT_OD);   // SDC_SS   (3 -> 1)
  configure_gpio(PORT_B, GPIO_13, GPIO_AF_PP);    // SDC_MISO (4 <- 7)
  configure_gpio(PORT_B, GPIO_14, GPIO_AF_PP);    // SDC_MOSI (5 -> 2)
  configure_gpio(PORT_B, GPIO_15, GPIO_AF_PP);    // SDC_SCK  (6 -> 5)
  set_gpio(PORT_B, GPIO_12, 1);                   // disable SDC_SS
#endif /* HAVE_SDC */
#endif  /* APM_PICKUP */

#if (0 != HAVE_USB)  // FTODO ask Maurizio check if only usb
  GCR1.field.usb_pad_en = 1;
  //GCR1.field.vbuslow = 1;	LS patch
  /* GCR1.field.vbusses = 1;  //starting, it must be 0; after usb initialization it should goes 1 */
  //GCR1.field.vbusval = 1; LS patch
#endif

  EIC_ICR.field.irq_en = 0;
  EIC_IER = 0x00000000;
  
}

/******************************************************************************/
/* Function:  ResetEIC                                                        */
/*                                                                            */
/*! \brief    Initialize the Enhanced Interrupt Controller
 *  \param    void
 *  \return   void
 *  \remark   IRQ are disabled on exit. OS20 will enable when ready
 */
/******************************************************************************/
void ResetEic(void)
{
  volatile uint32 isr_addr;

  GCR1.field.eic_sres = 1;
  GCR1.field.eic_sres = 0;

  isr_addr = (uint32)REENT_INT_IRQ;
  EIC_SIR_0.all = (isr_addr << 16); //| 0x0F;
  EIC_SIR_1.all = (isr_addr << 16); //| 0x0F;
  EIC_SIR_2.all = (isr_addr << 16); //| 0x0F;
  EIC_SIR_3.all = (isr_addr << 16); //| 0x0F;
  EIC_SIR_4.all = (isr_addr << 16); //| 0x0F;
  EIC_SIR_5.all = (isr_addr << 16); //| 0x0F;
  EIC_SIR_6.all = (isr_addr << 16); //| 0x0F;
  EIC_SIR_7.all = (isr_addr << 16); //| 0x0F;
  EIC_SIR_8.all = (isr_addr << 16); //| 0x0F;
  EIC_SIR_9.all = (isr_addr << 16); //| 0x0F;
  EIC_SIR_10.all = (isr_addr << 16); //| 0x0F;
  EIC_SIR_11.all = (isr_addr << 16); //| 0x0F;
  EIC_SIR_12.all = (isr_addr << 16); //| 0x0F;
  EIC_SIR_13.all = (isr_addr << 16); //| 0x0F;
  EIC_SIR_14.all = (isr_addr << 16); //| 0x0F;
  EIC_SIR_15.all = (isr_addr << 16); //| 0x0F;
  EIC_SIR_16.all = (isr_addr << 16); //| 0x0F;
  EIC_SIR_17.all = (isr_addr << 16); //| 0x0F;
  EIC_SIR_18.all = (isr_addr << 16); //| 0x0F;
  EIC_SIR_19.all = (isr_addr << 16); //| 0x0F;
  EIC_SIR_20.all = (isr_addr << 16); //| 0x0F;
  EIC_SIR_21.all = (isr_addr << 16); //| 0x0F;
  EIC_SIR_22.all = (isr_addr << 16); //| 0x0F;
  EIC_SIR_23.all = (isr_addr << 16); //| 0x0F;
  EIC_SIR_24.all = (isr_addr << 16); //| 0x0F;
  EIC_SIR_25.all = (isr_addr << 16); //| 0x0F;
  EIC_SIR_26.all = (isr_addr << 16); //| 0x0F;
  EIC_SIR_27.all = (isr_addr << 16); //| 0x0F;
  EIC_SIR_28.all = (isr_addr << 16); //| 0x0F;
  EIC_SIR_29.all = (isr_addr << 16); //| 0x0F;
  EIC_SIR_30.all = (isr_addr << 16); //| 0x0F;
  EIC_SIR_31.all = (isr_addr << 16); //| 0x0F;
  EIC_IVR.all = isr_addr;

  //EIC_ICR.field.irq_en = 1;
}

/******************************************************************************/
/* Function:  rccu_init                                                       */
/*                                                                            */
/*! \brief    Initialize the Reset and Clock Control Unit
 *  \param    void