📄 srvchn.c
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if (OIF_EXT_CLOCK_ON) { //MISC1.field.gpio_oni2s = 0; /* BB041014 */ oif_freq = OIF_EXT_CLOCK_FREQ; if (oif_freq > 0x10) { oif_freq = 0x10; } } else#endif { //MISC1.field.gpio_oni2s = 1; /* BB041014 */ oif_freq = 0x10; } /* select OIF disk speed */ switch (oif_ttm_speed & DISC_MODE) { case CLV: switch (oif_ttm_speed & DISC_SPEED) { case CLV_1X: oif_speed = 0; break; case CLV_2X: oif_speed = 1; break; //case CLV_4X: default: oif_speed = 2; break; } break; //case CAV: default: oif_speed = 3; break; } /* select OIF I2S frame length */ oif_frm_len = OIF_I2S_FRAME_LEN; if (oif_frm_len > OIF_I2S_FRAME_LEN_32) { oif_frm_len = OIF_I2S_FRAME_LEN_16; } oif_mode.analog = (uint8)(OIF_ANALOG_ON ? 1 : 0); oif_mode.spdif = (uint8)((OIF_SPDIF_ON && spdif_out_ratio[oif_freq][oif_speed]) ? 1 : 0); oif_mode.i2s = (uint8)((OIF_I2S_ON && i2s_out_ratio[oif_freq][oif_speed][oif_frm_len]) ? 1 : 0); if (0 == oif_mode.i2s) /* BB041007f */ { oif_frm_len = OIF_I2S_FRAME_LEN_16; } if (0 != oif_mode.spdif) { GCR1.field.spdif_sel = 1; // 1->SPDIF is Selected OIF_SELECT_SPDIF(); } else { GCR1.field.spdif_sel = 0; // 0->I2S is Selected OIF_SELECT_I2S(); } OIF_SOFT_RST.all = 0xFF; // BBTODO check if needed ECC_MODE.field.acon = OIF_AUDIO_CONCEALMENT; /* turn off all */ OIF_AP_MUTE_CTRL.all = MUTE_I2S_OFF | MUTE_I2S_FORCE | MUTE_SPDIF_OFF | MUTE_SPDIF_FORCE; if (OIF_AUDIO_MODE) { OIF_AP_CONTROL_PART_1.all = 0xA0; //OIF_AP_CONTROL_PART_1.field.current_data_shift = 0x00; //OIF_AP_CONTROL_PART_1.field.data_signed_ext = 1; //OIF_AP_CONTROL_PART_1.field.audio_enable = 1; } else { OIF_AP_CONTROL_PART_1.all = 0x20; //OIF_AP_CONTROL_PART_1.field.current_data_shift = 0x00; //OIF_AP_CONTROL_PART_1.field.data_signed_ext = 1; //OIF_AP_CONTROL_PART_1.field.audio_enable = 0; } OIF_AP_CONTROL_PART_2.all = 0x98; //OIF_AP_CONTROL_PART_2.field.target_data_shift = 0x18; //OIF_AP_CONTROL_PART_2.field.enable_deemphasis = 0; //OIF_AP_CONTROL_PART_2.field.enable_equalizer = 0; //OIF_AP_CONTROL_PART_2.field.enable_sample_req = 1; OIF_SPDIF_CONTROL.field.i2s_spdif_mux = 1; OIF_I2S_SPDIF_REG_1.mux_1_field.i2s_data_out_format = OIF_I2S_SWAPPING_MODE(oif_frm_len); OIF_I2S_SPDIF_REG_0.mux_1_field.slsi_pi2s = OIF_I2S_SLSI; OIF_I2S_SPDIF_REG_0.mux_1_field.sclk_level = (uint8)(OIF_I2S_SCLK_LEV ? 0 : 1); /* BB040929b */ OIF_I2S_SPDIF_REG_0.mux_1_field.wclk_level = (uint8)(OIF_I2S_WCLK_LEV ? 0 : 1); /* BB040929b */ OIF_I2S_SPDIF_REG_0.mux_1_field.c2flags_level = OIF_I2S_C2FL_LEV; OIF_I2S_SPDIF_REG_0.mux_1_field.sdata_level = OIF_I2S_DATA_LEV; OIF_I2S_SPDIF_REG_0.mux_1_field.framelength = oif_frm_len; OIF_I2S_SPDIF_REG_2.all = 0x70; //OIF_I2S_SPDIF_REG_2.mux_1_field.ad_mute = 1; //OIF_I2S_SPDIF_REG_2.mux_1_field.parallel_mode = 1; //OIF_I2S_SPDIF_REG_2.mux_1_field.ad_mclk_polarity = 1; OIF_SPDIF_CONTROL.field.i2s_spdif_mux = 0; OIF_SPDIF_CONTROL.field.spdif_data_mode = 1; OIF_SPDIF_CONTROL.field.validity_mux = 1;//BB041022b OIF_I2S_SPDIF_REG_2.mux_0_field.extern_clock_mux = OIF_EXT_CLOCK_ON; OIF_I2S_SPDIF_REG_2.mux_0_field.i2s_ratio = i2s_out_ratio[oif_freq][oif_speed][oif_frm_len]; if (OIF_I2S_SPDIF_REG_2.mux_0_field.i2s_ratio) { switch (oif_frm_len) { case OIF_I2S_FRAME_LEN_32: OIF_I2S_SPDIF_REG_2.mux_0_field.word_ratio = 3; break; case OIF_I2S_FRAME_LEN_24: OIF_I2S_SPDIF_REG_2.mux_0_field.word_ratio = 2; break; //case OIF_I2S_FRAME_LEN_16: default: OIF_I2S_SPDIF_REG_2.mux_0_field.word_ratio = 1; break; } } else { OIF_I2S_SPDIF_REG_2.mux_0_field.word_ratio = 0; } OIF_I2S_SPDIF_REG_1.mux_0_field.invert_clock = 0; if (OIF_EXT_CLOCK_ON) { OIF_I2S_SPDIF_REG_1.mux_0_field.input_clock_selection = 3; } else { OIF_I2S_SPDIF_REG_1.mux_0_field.input_clock_selection = 2; } OIF_I2S_SPDIF_REG_1.mux_0_field.spdif_ratio = spdif_out_ratio[oif_freq][oif_speed]; if ((oif_ttm_speed & DISC_MODE) == CLV) { OIF_AP_STATUS.field.underflow_mode = 1; } else { OIF_AP_STATUS.field.underflow_mode = 3; }/* OIF_AP_STATUS.field.en_int_undf = 1; OIF_AP_STATUS.field.en_int_short_frame = 1; OIF_AP_STATUS.field.en_int_long_frame = 1;*/ oif_mute = MUTE_I2S_FORCE | MUTE_SPDIF_FORCE; if (oif_mode.spdif) { switch (OIF_SPDIF_MUTE_MODE) { case CIS_MUTE_MODE_HZ: oif_mute |= MUTE_SPDIF_MODE_HZ; break; case CIS_MUTE_MODE_LOW: oif_mute |= MUTE_SPDIF_MODE_LOW; break; default: oif_mute |= MUTE_SPDIF_MODE_DATA; break; } } else { oif_mute |= MUTE_SPDIF_OFF; } if (oif_mode.i2s) { switch (OIF_I2S_MUTE_MODE) { case CIS_MUTE_MODE_HZ: oif_mute |= MUTE_I2S_MODE_HZ; break; case CIS_MUTE_MODE_LOW: oif_mute |= MUTE_I2S_MODE_LOW; break; default: oif_mute |= MUTE_I2S_MODE_DATA; break; } } else { oif_mute |= MUTE_I2S_OFF; } OIF_SP_CTRL.field.mute_boundary_mode = 1;// Mute On Sector Boundary [MM] 05/09/06 OIF_AP_MUTE_CTRL.all = oif_mute; if (!oif_mode.audio_initialized) { oif_mode.audio_initialized = 1; // BBTODO check for I2S workaround } OIF_SOFT_RST.all = 0x00; // BBTODO check if needed DISABLE_INTERRUPTS(); if (oif_mute_control.audio_on) { audio_on(); } ENABLE_INTERRUPTS();}/******************************************************************************//* Function: oif_init *//* *//*! \brief Initialization of output interface(s) * \param void * \return void * \remark Sets OIF block into reset, calls CDTEXT_init and audio_init * enables oif interrupt *//******************************************************************************/void oif_init(void){ OIF_SOFT_RST.all = 0x00; CD_TEXT_CONTROL.all = 0x72; OIF_SP_CTRL.field.en_shockproof = 1; // To enable buffer Data OIF_SP_CTRL.field.monitor_buffer = 1; oif_requested_speed = CLV | CLV_1X; oif_ttm_speed = CLV | CLV_1X; initialize_audio(); OSAL_isr_install(OSAL_ISR_OIF, 0x0f, oif_isr_irq);}#else // APM_PICKUP#if 0void oif_init_keyboard(void){ GCR1.field.spdif_sel = 0; // 1->SPDIF is Selected // 0->I2S is selected OIF_SOFT_RST.all = 0xFF; OIF_SP_CTRL.field.en_shockproof = 0; // To enable Raw Data Output//OIF_SP_CTRL.field.en_shockproof = 1; // To enable buffer Data OIF_SP_CTRL.field.monitor_buffer = 1; OIF_AP_CONTROL_PART_2.field.enable_sample_req = 1; OIF_AP_CONTROL_PART_1.field.data_signed_ext = 1; OIF_I2S_SPDIF_REG_1.mux_0_field.spdif_ratio = 0x0C; OIF_I2S_SPDIF_REG_1.mux_0_field.input_clock_selection = 2; OIF_I2S_SPDIF_REG_1.mux_0_field.invert_clock = 1; OIF_SPDIF_CONTROL.field.i2s_spdif_mux = 1; OIF_I2S_SPDIF_REG_2.mux_1_field.parallel_mode = 1; OIF_I2S_SPDIF_REG_2.mux_1_field.ad_mute = 0; OIF_I2S_SPDIF_REG_0.mux_1_field.slsi_pi2s = 1; OIF_I2S_SPDIF_REG_0.mux_1_field.framelength = 1; // 24 bit //OIF_I2S_SPDIF_REG_0.mux_1_field.framelength = 0; // 16 bit OIF_I2S_SPDIF_REG_0.mux_1_field.sclk_level = 1; // 24 bit OIF_I2S_SPDIF_REG_0.mux_1_field.wclk_level = 1; // 24 bit OIF_I2S_SPDIF_REG_0.mux_1_field.c2flags_level = 0; // 24 bit OIF_I2S_SPDIF_REG_0.mux_1_field.sdata_level = 0; // 24 bit OIF_I2S_SPDIF_REG_1.mux_1_field.i2s_data_out_format = 5; OIF_SPDIF_CONTROL.field.i2s_spdif_mux = 0; OIF_I2S_SPDIF_REG_2.mux_0_field.i2s_ratio = 0x10; //24 bit Keyboard OIF_I2S_SPDIF_REG_2.mux_0_field.word_ratio = 2; // 24 bit Keyboard; OIF_I2S_SPDIF_REG_2.mux_0_field.extern_clock_mux = 1; OIF_SPDIF_CONTROL.field.spdif_data_mode = 1; OIF_SPDIF_CONTROL.field.spdif_efm_mode = 1; // Enable Audio DAC OIF_SPDIF_CONTROL.field.i2s_spdif_mux = 1; OIF_I2S_SPDIF_REG_2.mux_1_field.parallel_mode = 1; OIF_I2S_SPDIF_REG_2.mux_1_field.ad_mute = 0; OIF_I2S_SPDIF_REG_2.mux_1_field.ad_mclk_polarity = 1; OIF_I2S_SPDIF_REG_0.mux_1_field.slsi_pi2s = 1; // Keyboard OIF_I2S_SPDIF_REG_0.mux_1_field.framelength = 1; // Keyboard OIF_I2S_SPDIF_REG_0.mux_1_field.sclk_level = 1; // Keyboard OIF_I2S_SPDIF_REG_0.mux_1_field.wclk_level = 0; // Keyboard OIF_I2S_SPDIF_REG_0.mux_1_field.c2flags_level = 0; // Keyboard OIF_I2S_SPDIF_REG_0.mux_1_field.sdata_level = 0; // Keyboard OIF_I2S_SPDIF_REG_0.mux_1_field.audio_dac_clk = 0; OIF_I2S_SPDIF_REG_1.mux_1_field.i2s_data_out_format = 5; // Keyboard OIF_SPDIF_CONTROL.field.i2s_spdif_mux = 0; OIF_SOFT_RST.all = 0x00;}#endif // if 0void oif_init(void){ volatile CIF_CONF_UNION cif_conf; DISABLE_INTERRUPTS(); // Start OIF Reconfiguration // Save Channel Interface Configuration cif_conf.all = CIF_CONF.all; // Channel Output ITF under H/W reset CGC_PUR1.field.ch_itf = 0; CGC_PCG1.field.ch_itf = 0; // OIF under H/W reset. AAB_PUR0.field.oif = 0; AAB_PCG0.field.oif = 0; // Release Channel ITF from H/W reset CGC_PUR1.field.ch_itf = 1; CGC_PCG1.field.ch_itf = 1; // Restore CIF Configuration CIF_CONF.all = cif_conf.all; // Set CIF_CONF.SRC bit // To give data to the OIF in order to set 1 // The enable_sample_request. if(!cif_conf.field.src) { CIF_CONF.field.src = 1; } // Block Decoder under H/W Reset AAB_PUR0.field.block_dec = 0; // Release OIF From Reset AAB_PUR0.field.oif = 1; AAB_PCG0.field.oif = 1; // Program OIF // After OIF Reset en_shockproof is 0. // OIF Request sample directly from CIRC // To be sure that OIF request data directly from Channel Interface // Output Port do the following procedure // Set en_shockproof = 1 OIF_SP_CTRL.field.en_shockproof = 1; #if (HAVE_CD_MECHA == 1) // H/W Reset CIRC/CLV Hardware Block AAB_PUR0.field.circ_clv = 0; AAB_PUR0.field.circ_clv = 1;#endif // H/W Reset Block Decoder AAB_PUR0.field.block_dec = 1; // Reinitialize ClV, ECC and Block Decoder #if (HAVE_CD_MECHA == 1) clv_init();#endif ecc_init(); bd_dma_init(&bd_params); //BD_CTL1.field.test = 0x01; // For Testing OIF_AP_CONTROL_PART_2.field.enable_sample_req = 1; // OIF_SP_CTRL.field.en_shockproof = 0; // To enable buffer Data OIF_SP_CTRL.field.monitor_buffer = 1; // OIF_AP_CONTROL_PART_2.field.enable_sample_req = 0; OIF_AP_CONTROL_PART_1.field.data_signed_ext = 1; OIF_AP_CONTROL_PART_1.field.audio_enable = 1; OIF_I2S_SPDIF_REG_1.mux_0_field.spdif_ratio = 0x0C; OIF_I2S_SPDIF_REG_1.mux_0_field.input_clock_selection = 2; OIF_I2S_SPDIF_REG_1.mux_0_field.invert_clock = 1; switch(CNF_I2S_FS) { case FS_32: OIF_I2S_SPDIF_REG_2.mux_0_field.i2s_ratio = 0x18; OIF_I2S_SPDIF_REG_2.mux_0_field.word_ratio = 1; break; case FS_48: OIF_I2S_SPDIF_REG_2.mux_0_field.i2s_ratio = 0x10; OIF_I2S_SPDIF_REG_2.mux_0_field.word_ratio = 2; break; case FS_64: OIF_I2S_SPDIF_REG_2.mux_0_field.i2s_ratio = 0x0C; OIF_I2S_SPDIF_REG_2.mux_0_field.word_ratio = 3; break; default: OIF_I2S_SPDIF_REG_2.mux_0_field.i2s_ratio = 0x18; OIF_I2S_SPDIF_REG_2.mux_0_field.word_ratio = 1; break; } OIF_I2S_SPDIF_REG_2.mux_0_field.extern_clock_mux = 1; // I2S OIF_SPDIF_CONTROL.field.i2s_spdif_mux = 1; OIF_I2S_SPDIF_REG_0.mux_1_field.slsi_pi2s = CNF_I2S_FORMAT; // philips i2s switch(CNF_I2S_FS) { case FS_32: OIF_I2S_SPDIF_REG_0.mux_1_field.framelength = 0; break; case FS_48: OIF_I2S_SPDIF_REG_0.mux_1_field.framelength = 1; break; case FS_64:
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