blspidrv.c

本程序为ST公司开发的源代码

/**************************(c) STMicroelectronics *****************************/
/*! \file
 *
 * CVS ID:   $Id: blspidrv.c,v 1.13 2007/09/03 14:21:59 marcucci Exp $
 * Author:   Maurizio Marcucci [MM] - STM
 * Date:     $Date: 2007/09/03 14:21:59 $
 * Revision: $Revision: 1.13 $
 *
 *  Project Scope:  CDM M8
 *
 *  Organisation:   Optical Media Storage B.U.
 *                  AGRATE ITALY Application Lab
 *
 *  Version Control:
 *    \source       main/spidrv.c
 *    \version      0.1
 *    \author       ST Agrate
 *    \date         00-00-00
 *
 *******************************************************************************
 *  \brief          Definition of Debug Procedures
 *
 *  \par            Change History:
 *
 * - PH040616       Fixed service command SVC_TTM_x_HZ
 * - PH040803       Changes:
 *                  - Reorganisation service mode variables
 *                  - BER measurement
 * - BB040923a      Code rom and ram size optimisation:
 *                  - only one type of seek function are compiled (MFS or SID)
 *
 ***************************************************
 *
 * STM CVS Log:
 *
 * $Log: blspidrv.c,v $
 * Revision 1.13  2007/09/03 14:21:59  marcucci
 * Removed Compiler Warning
 *
 * Revision 1.12  2007/07/13 11:05:12  marcucci
 * Initilaize BSPI only when it is necessary
 *
 * Revision 1.11  2007/02/15 13:10:32  marcucci
 * Bootloader Optimization
 *
 * Revision 1.10  2006/10/05 14:21:56  belardi
 * Changed last for() with bl_delay()
 *
 * Revision 1.9  2006/09/18 09:55:20  belardi
 * Corrected CVS keyword usage
 *
 * Revision 1.8  2006/09/18 09:22:15  belardi
 * Added Log CVS keyword into file header
 *
 *
 ******************************************************************************/

#include "blgendef.h"
#include "blmsgdef.h"
#include "bldbgdef.h"
#include "hwreg.h"
#include "blscidef.h"



//extern uint32 Install_ISR(uint32 isr, uint32 vct);
//extern __irq void tim0_isr_hdl(void);
extern __irq void bl_bspi_glb_isr(void);
//void start_timer(uint32 TimeOut);
//uint32 check_timer(void);
//void stop_timer(void);

extern void configure_gpio(unsigned int port, unsigned int bit, unsigned int function);
//void pcintf(uint32 sf_download_status);
//extern void swi_isr(void);
//extern void MIRROR_JUMP(void);
//extern void CODE_JUMP(void);
//extern void Remap(void);
//void configure_gpio(unsigned int port, unsigned int bit, unsigned int function);
void bl_set_gpio(unsigned int port, unsigned int bit, unsigned int val);
//void remap(void);
//void InterruptEnable(void);
//void pcint_init(void);
void bl_bspi_init(BL_BSPI_STRUCT * bl_bspi_ptr);
void bl_bspi_send(uint32 data);
uint32 bl_bspi_rdid(BL_BSPI_STRUCT * bl_bspi_ptr);
uint32 bl_bspi_rdsr(BL_BSPI_STRUCT * bl_bspi_ptr);
uint32 bl_bspi_bulk_erase(BL_BSPI_STRUCT * bl_bspi_ptr);
uint32 bl_bspi_wren(BL_BSPI_STRUCT * bl_bspi_ptr);
void bl_bspi_pp(uint32 bl_page_addr, uint32 bl_byte_no, BL_BSPI_STRUCT * bl_bspi_ptr);
uint32 bl_sf_erase(BL_BSPI_STRUCT * bl_bspi_ptr);
uint32 bl_sf_pp(uint32 bl_page_addr, uint32 bl_byte_no, BL_BSPI_STRUCT * bl_bspi_ptr);
void bl_sf_read(uint32 bl_page_addr, uint32 bl_byte_no, BL_BSPI_STRUCT * bl_bspi_ptr);
void bl_start_timer(uint32 bl_TimeOut);
//uint32 CopyProgramToRam(void);
//void ClearProgramRam(void);
//void rccu_init(void);
//void timer0_init(void);
//void timer_test(void);
//void switch_off_pll(void);

//void enable_clock(void);

extern BL_STRUCT * bl;


__forceinline void bl_select_sf(void)
{
  PDB &= 0xFFFFFFFE;
}

__forceinline void bl_unselect_sf(void)
{
  PDB |= 1;
}

__forceinline void bl_delay(int32 i)
{
  for (; i > 0; i--) // BBTODO what happen if optimized?
    ;
}

void bl_bspi_init(BL_BSPI_STRUCT *bl_bspi_ptr)
{
  uint32 bl_isr_addr;
  //uint32 i;
  configure_gpio(BL_PORT_B, BL_GPIO_0, BL_GPIO_OUT_PP); // SFLASH_SS
  
  bl->error_reason = 0;
  //bl_sf_debug_idx = 0;

  #if 0
  for(i = 0; i < 256; i++)
  {
   bl->bspi_tx_buffer[i] = (i & 0xFF);
  }
  #endif

  bl_bspi_ptr->bspi_ovfl_cntr = 0;
  bl_bspi_ptr->bspi_berr_cntr = 0;

  bl_bspi_ptr->bspi_rx_bytes = 0;
  //set_gpio(PORT_B, GPIO_0, 1);
  bl_unselect_sf();
  BSPI_CSR1.field.bspe = 0;    // BSPI Disable
  //BSPI_CLK = 100;              // Fcpu/BSPI_CLK
  BSPI_CLK = 34;              // Fcpu/BSPI_CLK
  BSPI_CSR1.field.mstr = 1;    // BSPI is a master
  BSPI_CSR2.field.dfifo = 1;   //Clear FIFO
  BSPI_CSR3.field.mask_ss = 1; // Mask SS
  BSPI_CSR1.field.cpol = 0;
  BSPI_CSR1.field.cpha = 0;

  BSPI_CSR1.field.rfs = 16; // 16 Word FIFO
  BSPI_CSR1.field.wl = 0;   // 8 bit Data Added to re-write the reset value
  BSPI_CSR1.field.rie = 1;  // Receive FIFO Not Empty
  BSPI_CSR2.field.tfs = 16; // 16 Words Tx FIFO


  BSPI_CSR1.field.reie = 0; // Receive Error Interrupt Enable
  BSPI_CSR1.field.beie = 0;   // Bus Error Interrupt Disabled
  BSPI_CSR2.field.tie = 0;    // Transmit FIFO Interrupt Disabled , Added to re-write the Reset Value
  BSPI_CSR3.field.dma_en = 0; // DMA Disabled
  BSPI_CSR3.field.tburst_len = 0;
  BSPI_CSR3.field.rburst_len = 0;
  BSPI_CSR3.field.treq_len = 0;
  BSPI_CSR3.field.rreq_len = 0;




  bl_isr_addr = (uint32) bl_bspi_glb_isr;
  EIC_SIR_6.all =  (bl_isr_addr << 16) | 0x0F;
  EIC_IVR.all =  bl_isr_addr;
  EIC_IER |=  BL_BSPI_GLB_INT_MASK;

  //BSPI_CSR1.field.bspe = 1; // BSPI Enable
}


void bl_bspi_send(uint32 bl_data)
{
  while(1)
  {
   if(BSPI_CSR2.field.tfe)
   {
     BSPI_TXR = (bl_data << 8);
     break;
   }
  }

}


uint32 bl_bspi_rdid(BL_BSPI_STRUCT * bl_bspi_ptr)
{
  bl_bspi_ptr->bspi_rx_buffer_idx = 0;
  bl_select_sf();
  //set_gpio(PORT_B, GPIO_0, 0);
  bl_delay(100);
  bl_bspi_send(0xAB);
  bl_bspi_send(0x00); // 1st Dummy
  bl_bspi_send(0x00); // 2nd Dummy
  bl_bspi_send(0x00); // 3rd Dummy
  bl_bspi_send(0x00); // Read
  bl_delay(100);
  //while(bspi_rx_buffer_idx != 5);
  while (1)
  {
    if (bl_bspi_ptr->bspi_rx_buffer_idx == 5)
    {
      break;
    }
  }

  bl_unselect_sf();
  //set_gpio(PORT_B, GPIO_0, 1);
  return bl_bspi_ptr->bspi_rx_buffer[4];
}


uint32 bl_bspi_rdsr(BL_BSPI_STRUCT * bl_bspi_ptr)
{
  bl_bspi_ptr->bspi_rx_buffer_idx = 0;
  bl_select_sf();
  //set_gpio(PORT_B, GPIO_0, 0);
  bl_delay(100);
  bl_bspi_send(0x05);
  bl_bspi_send(0x00); // 1st Dummy
  bl_delay(100);
  //while(bspi_rx_buffer_idx != 2);

  while (1)
  {
    if (bl_bspi_ptr->bspi_rx_buffer_idx == 2)
    {
      break;
    }
  }
  bl_unselect_sf();
  //set_gpio(PORT_B, GPIO_0, 1);
  return bl_bspi_ptr->bspi_rx_buffer[1];
}

uint32 bl_bspi_wren(BL_BSPI_STRUCT * bl_bspi_ptr)
{
  bl_bspi_ptr->bspi_rx_buffer_idx = 0;
  bl_select_sf();
  //set_gpio(PORT_B, GPIO_0, 0);
  bl_delay(100);
  bl_bspi_send(0x06);
  bl_delay(100);
  //while(bspi_rx_buffer_idx != 1);
  while (1)
  {
    if (bl_bspi_ptr->bspi_rx_buffer_idx == 1)
    {
      break;
    }
  }

  bl_unselect_sf();
  //set_gpio(PORT_B, GPIO_0, 1);
  return bl_bspi_ptr->bspi_rx_buffer[0];
}


uint32 bl_bspi_bulk_erase(BL_BSPI_STRUCT * bl_bspi_ptr)
{
  bl_bspi_ptr->bspi_rx_buffer_idx = 0;
  bl_select_sf();
  //set_gpio(PORT_B, GPIO_0, 0);
  bl_delay(100);
  bl_bspi_send(0xC7);
  bl_delay(100);
  //while(bspi_rx_buffer_idx != 1);
  while (1)
  {
    if (bl_bspi_ptr->bspi_rx_buffer_idx == 1)
    {
      break;
    }
  }
  bl_unselect_sf();
  //set_gpio(PORT_B, GPIO_0, 1);
  return bl_bspi_ptr->bspi_rx_buffer[0];
}

void bl_bspi_pp(uint32 bl_page_addr, uint32 bl_byte_no, BL_BSPI_STRUCT * bl_bspi_ptr)
{
 uint32 i;
 uint32 bl_byte_0;
 uint32 bl_byte_1;
 uint32 bl_byte_2;

 bl_byte_0 = (bl_page_addr & 0xFF);
 bl_byte_1 = (bl_page_addr & 0xFF00) >> 8;
 bl_byte_2 = (bl_page_addr & 0xFF0000) >> 16;

  bl_bspi_ptr->bspi_rx_buffer_idx = 0;
  bl_select_sf();
  //set_gpio(PORT_B, GPIO_0, 0);
  bl_delay(100);
  bl_bspi_send(0x02);
  bl_bspi_send(bl_byte_2);
  bl_bspi_send(bl_byte_1);
  bl_bspi_send(bl_byte_0);
  bl_delay(10);
  for (i = 0; i < bl_byte_no; i++)
  {
    bl_bspi_send(bl_bspi_ptr->bspi_tx_buffer[i]);
  }
  bl_delay(100);
  //while(bspi_rx_buffer_idx != (byte_no + 4));
  while (1)
  {
    if (bl_bspi_ptr->bspi_rx_buffer_idx == (bl_byte_no + 4))
    {
      break;
    }
  }
  bl_unselect_sf();
  //set_gpio(PORT_B, GPIO_0, 1);
}


uint32 bl_sf_erase(BL_BSPI_STRUCT * bl_bspi_ptr)
{
 bl_bspi_wren(bl_bspi_ptr);

 bl_bspi_ptr->sf_sr = bl_bspi_rdsr(bl_bspi_ptr);

 //bl_sf_debug[bl_sf_debug_idx++] = bl_sf_sr | 0x80000000;
 //bl_sf_debug_idx &= 0x0F;

 if((bl_bspi_ptr->sf_sr & 0x02) == 0x02)
 {
  bl_bspi_bulk_erase(bl_bspi_ptr);
  while(1)
  {
   bl_bspi_ptr->sf_sr = bl_bspi_rdsr(bl_bspi_ptr);
   //bl_sf_debug[bl_sf_debug_idx++] = bl_sf_sr | 0x4000000;
   //bl_sf_debug_idx &= 0x0F;
   if((bl_bspi_ptr->sf_sr & 0x01) == 0x00)
   {
    return 1;
   }
  }
 }
 else
 {
   return 0;
 }

}



uint32 bl_sf_pp(uint32 bl_page_addr, uint32 bl_byte_no, BL_BSPI_STRUCT * bl_bspi_ptr)
{
 bl_bspi_wren(bl_bspi_ptr);

 bl_bspi_ptr->sf_sr = bl_bspi_rdsr(bl_bspi_ptr);

 //bl_sf_debug[bl_sf_debug_idx++] = bl_sf_sr | 0x80000000;
 //bl_sf_debug_idx &= 0x0F;

 if((bl_bspi_ptr->sf_sr & 0x02) == 0x02)
 {
  bl_bspi_pp(bl_page_addr, bl_byte_no, bl_bspi_ptr);
  while(1)
  {
   bl_bspi_ptr->sf_sr = bl_bspi_rdsr(bl_bspi_ptr);
   //bl_sf_debug[bl_sf_debug_idx++] = bl_sf_sr | 0x4000000;
   //bl_sf_debug_idx &= 0x0F;
   if((bl_bspi_ptr->sf_sr & 0x01) == 0x00)
   {
    return 1;
   }
  }
 }
 else
 {
   return 0;
 }

}



void bl_sf_read(uint32 bl_page_addr, uint32 bl_byte_no, BL_BSPI_STRUCT * bl_bspi_ptr)
{
 uint32 i;

 uint32 bl_byte_0;
 uint32 bl_byte_1;
 uint32 bl_byte_2;

 bl_byte_0 = (bl_page_addr & 0xFF);
 bl_byte_1 = (bl_page_addr & 0xFF00) >> 8;
 bl_byte_2 = (bl_page_addr & 0xFF0000) >> 16;

 bl_bspi_ptr->bspi_rx_buffer_idx = 0;
  bl_select_sf();
 //set_gpio(PORT_B, GPIO_0, 0);
 bl_delay(100);
 bl_bspi_send(0x03);
 bl_bspi_send(bl_byte_2);
 bl_bspi_send(bl_byte_1);
 bl_bspi_send(bl_byte_0);
 bl_delay(10);
 for(i= 0; i < bl_byte_no; i++)
 {
  bl_bspi_send(0x00);
 }
 bl_delay(100);
 //while(bspi_rx_buffer_idx != (byte_no + 4));
 while(1)
 {
  if(bl_bspi_ptr->bspi_rx_buffer_idx == (bl_byte_no + 4))
  {
   break;
  }
 }
 bl_unselect_sf();
 //set_gpio(PORT_B, GPIO_0, 1);
}