📄 blgendef.h
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/**************************************************
*
* blgendef.h
*
* CVS ID: $Id: blgendef.h,v 1.15 2007/07/11 10:12:11 marcucci Exp $
* Author: Maurizio Marcucci [MM] - STM
* Date: $Date: 2007/07/11 10:12:11 $
* Revision: $Revision: 1.15 $
*
* Description:
*
*
***************************************************
*
* COPYRIGHT (C) ST Microelectronics 2005
* All Rights Reserved
*
***************************************************
*
* STM CVS Log:
*
* $Log: blgendef.h,v $ * Revision 1.15 2007/07/11 10:12:11 marcucci * Set BUSY condition on I2C Start Detection and I2C emergency Init added * * Revision 1.14 2007/07/04 14:22:29 marcucci * Continuous Data Transfer Added *
* Revision 1.13 2007/07/02 08:40:30 marcucci
* I2C Bootloader
*
* Revision 1.12 2007/02/15 13:09:32 marcucci
* Bootloader Optimization
*
* Revision 1.11 2006/11/08 08:49:14 marcucci
* Add one define for HAVE_UPDATE
*
* Revision 1.10 2006/10/23 08:59:37 marcucci
* Addede some definition for ctr_update_transition
*
* Revision 1.9 2006/09/18 09:55:20 belardi
* Corrected CVS keyword usage
*
* Revision 1.8 2006/09/18 09:22:15 belardi
* Added Log
CVS keyword into file header
*
*
***************************************************/
#ifndef _BLGENDEF_H
#define _BLGENDEF_H
#include "accordoptypes.h"
#include "i2cdef.h"
#include "uartdef.h"
#include "blvardef.h"
#define BL_CHIP_TYPE 1
#define BL_MV28 1
#define BL_V505 0
#define BL_MP25P40 0
#define BL_MP25P05 1
// BL_BOOT_MV28_TEST
// 0 -> Debugging
// 1 -> ROM Code
#define BL_ROM_CODE 1
// UART Selection for Bootloader
// 0 -> UART 0
// 1 -> UART 1
#define BL_UART 1
#define BL_DWN_CODE_2_RAM_A 0x01
#define BL_EXECUTE_CODE_FROM_EXP_RAM 0x02
#define BL_UND_VCT_TBL_IDX 0x04
#define BL_SWI_VCT_TBL_IDX 0x08
#define BL_PAB_VCT_TBL_IDX 0x0C
#define BL_DAB_VCT_TBL_IDX 0x10
#define BL_RES_VCT_TBL_IDX 0x14
#define BL_IRQ_VCT_TBL_IDX 0x18
#define BL_FIQ_VCT_TBL_IDX 0x1C
//#define AUDIO_ENABLE
//#define SEND_VCD
//#define PRINT_SUBCODE
#define BL_BD_XFER_IDLE 0x00
#define BL_BD_XFER_ACTIVE 0x01
#define BL_BD_XFER_COMPLETED 0x02
#define BL_BD_STOP_REQUESTED 0x03
#define BL_EIC_EXTINT0_MASK 0x00000001 // 0000 0000 0000 0000 0000 0000 0000 0001 IRQ 0
#define BL_EIC_EXTINT5_MASK 0x00000001 // 0000 0000 0000 0000 0000 0000 0010 0000 IRQ 5
#define BL_EIC_EFT0_MASK 0x20000000 // 0010 0000 0000 0000 0000 0000 0000 0000 IRQ 29
#define BL_EIC_UART0_MASK 0x00000080 // 0000 0000 0000 0000 0000 0000 1000 0000 IRQ 7
#define BL_EIC_UART1_MASK 0x00000100 // 0000 0000 0000 0000 0000 0001 0000 0000 IRQ 8
#define BL_EIC_I2C1_ERR_MASK 0x00000800 // 0000 0000 0000 0000 0000 1000 0000 0000 IRQ 11
#define BL_EIC_I2C1_DDC_MASK 0x00001000 // 0000 0000 0000 0000 0001 0000 0000 0000 IRQ 12
#define BL_EIC_I2C_EVENT_MASK 0x00000200 // 0000 0000 0000 0000 0000 0010 0000 0000 IRQ 9
#define BL_EIC_I2C_XFER_MASK 0x00000400 // 0000 0000 0000 0000 0000 0100 0000 0000 IRQ 10
#define BL_EIC_DMA_GLB_MASK 0x00040000 // 0000 0000 0000 0100 0000 0000 0000 0000 IRQ 18
#define BL_EIC_DMA_CH0_MASK 0x00080000 // 0000 0000 0000 1000 0000 0000 0000 0000 IRQ 19
#define BL_EIC_DMA_CH1_MASK 0x00100000 // 0000 0000 0001 0000 0000 0000 0000 0000 IRQ 20
#define BL_BD_GLB_MASK 0x00400000 // 0000 0000 0100 0000 0000 0000 0000 0000 IRQ 22
#define BL_SRC_DATA_FULL_INT_MASK 0x00010000 // 0000 0000 0000 0001 0000 0000 0000 0000 IRQ 16
#define BL_SRC_DATA_EMPTY_INT_MASK 0x00020000 // 0000 0000 0000 0010 0000 0000 0000 0000 IRQ 17
#define BL_BL_SRC_ERROR_INT_MASK 0x00008000 // 0000 0000 0000 0000 1000 0000 0000 0000 IRQ 15
#define BL_EIC_WDT_INT_MASK 0x80000000 // 1000 0000 0000 0000 0000 0000 0000 0000 IRQ 31
#define BL_BSPI_GLB_INT_MASK 0x00000040 // 0000 0000 0000 0000 0000 0000 0100 0000 IRQ 6
#define BL_SRC_DRE_CH 0
#define BL_SRC_DRF_CH 1
#define BL_BSPI_RX_CH 2
#define BL_BSPI_TX_CH 3
#define BL_CHITF_WR_CH 4
#define BL_CHITF_RD_CH 5
#define BL_EFT0_DMA_R_CH 6
#define BL_EFT1_DMA_R_CH 7
#define BL_DMA_PERIPHERAL_IS_THE_SOURCE 0
#define BL_DMA_PERIPHERAL_IS_THE_DESTINATION 1
#define BL_DMA_MEM_2_MEM 1
#define BL_DMA_WORD_SIZE_IS_BYTE 0
#define BL_DMA_WORD_SIZE_IS_HALF_WORD 1
#define BL_DMA_WORD_SIZE_IS_WORD 2
#define BL_DMA_BURST_IS_1_WORD 0
#define BL_DMA_BURST_IS_4_WORD 1
#define BL_DMA_BURST_IS_8_WORD 2
#define BL_DMA_BURST_IS_16_WORD 3
#define BL_DMA_NO_INCREMENT 0
#define BL_DMA_INCREMENT 1
#define BL_DMA_CH0 0
#define BL_DMA_CH1 1
#define BL_DMA_CH2 2
#define BL_DMA_CH3 3
//#define SRC_8K 4166 // At FAHB 33.33MHZ
#define BL_SRC_8K 8456 // At FAHB 67.64MHZ
#define BL_SRC_12K 2778 // At FAHB 33.33MHz
#define BL_SRC_16K 2080 // At FAHB 33.33MHz
#define BL_SRC_32K 1040 // At FAHB 33.33MHz
#define BL_SRC_48K 0x2B6 // At FAHB 33.33MHz
#define BL_SRC_DIRECT 0x00 // Input Sample rate 32K-44.1K
#define BL_SRC_DOWN 0x01 // Input Sample rate 44.1K-48K
#define BL_SRC_UPX2 0x02 // input Sample rate 16K-32K
#define BL_SRC_UPX4 0x03 // input Sample rate 8K-16K
#define BL_MASTER_I2C_ADDRESS 0x30
#define BL_I2C_WRITE 0
#define BL_I2C_READ 1
#define BL_RW_BIT_MASK 1
#define BL_TIMER0_BASE 16750
#define BL_GPIO_0 0
#define BL_GPIO_1 1
#define BL_GPIO_2 2
#define BL_GPIO_3 3
#define BL_GPIO_4 4
#define BL_GPIO_5 5
#define BL_GPIO_6 6
#define BL_GPIO_7 7
#define BL_GPIO_8 8
#define BL_RUN1 0x00
#define BL_RUN2 0x01
#define BL_RUN3 0x02
#define BL_PORT_A 1
#define BL_PORT_B 0
#define BL_GPIO_AF_PP 0
#define BL_GPIO_AF_OD 1
#define BL_GPIO_OUT_PP 2
#define BL_GPIO_OUT_OD 3
#define BL_GPIO_IN_OUT 4
#define BL_GPIO_IN 5
#define BL_TX_IDLE 0
#define BL_TX_START 1
#define BL_TX_ACTIVE 2
#define BL_TX_COMPLETE 3
//16Mbit SDRAM
#define BL_SDRAM_BASE_ADDR 0x80000000
#define BL_SDRAM_SIZE 0x60000 // 384Kbytes as ROM Size
#define BL_SDRAM_DWN_END_ADDR 0x80060000 // 384Kbytes as ROM Size
#define BL_SDRAM_SIZE_4_CODE_DWN 0x5FF00
#define BL_I2C_SDRAM_SIZE 0x20000 // 128Kbyte: 1Mbit
// We cannot Store More than 4Mbit
// Because SF is 4Mbit
#define BL_RAM_A_BASE_ADDR 0x40000000
#define BL_RAM_A_END_ADDR 0x40018000
#define BL_RAM_A_SIZE 0x18000 //96Kbytes
#define BL_RAM_A_SIZE_4_CODE_DWN 0x17F00
//#define BL_OVERLAY_START_ADDR 0x40014000 // 16K devoted for overlay
//#define BL_PATCH_AREA_SIZE (BL_OVERLAY_START_ADDR - BL_RAM_A_BASE_ADDR)
#define BL_PATCH_AREA_SIZE_4M BL_RAM_A_SIZE
#define BL_PATCH_AREA_SIZE_64K 0xA000 //40K
#define BL_PATCH_AREA_SIZE_1M 0x10000 //64K
//#define BL_OVERLAY_AREA_SIZE (BL_RAM_A_END_ADDR - BL_OVERLAY_START_ADDR)
//#define BL_OVERLAY_QTY 4
#define BL_EXP_RAM_BASE_ADDR 0xA0000000
#define BL_EXP_RAM_END_ADDR 0xA0060000 // 384kBytes as ROM Size
#define BL_EXP_RAM_SIZE 0x60000 // 384Kbytes as ROM Size
#define BL_EXP_RAM_SIZE_4_CODE_DWN 0x5FF00
//#define BL_SF_SIZE 0x80000
#define BL_SF_SIZE_4M 0x40000
#define BL_SF_SIZE_64K 0xE000
#define BL_SF_SIZE_1M 0x18000
#define BL_SF_DWN_INFO_SIZE 0x100
#define BL_SF_DATA_4_SDRAM_SIZE_4M (BL_SF_SIZE_4M - BL_PATCH_AREA_SIZE_4M - BL_SF_DWN_INFO_SIZE)
#define BL_SF_DATA_4_SDRAM_SIZE_64K (BL_SF_SIZE_64K - BL_PATCH_AREA_SIZE_64K - BL_SF_DWN_INFO_SIZE)
#define BL_SF_DATA_4_SDRAM_SIZE_1M (BL_SF_SIZE_1M - BL_PATCH_AREA_SIZE_1M - BL_SF_DWN_INFO_SIZE)
// Serial Flash Layout.
#define BL_SF_PATCH_AREA_START_ADDR 0x00000000
#define BL_SF_OVERLAY_AREA_START_ADDR_4M BL_PATCH_AREA_SIZE_4M
#define BL_SF_OVERLAY_AREA_START_ADDR_64K BL_PATCH_AREA_SIZE_64K
#define BL_SF_OVERLAY_AREA_START_ADDR_1M BL_PATCH_AREA_SIZE_1M
#define BL_SF_DWN_INFO_MV28 0x0005FF00
#define BL_SF_DWN_INFO_4M (BL_SF_SIZE_4M - BL_SF_DWN_INFO_SIZE)
#define BL_SF_DWN_INFO_64K (BL_SF_SIZE_64K - BL_SF_DWN_INFO_SIZE)
#define BL_SF_DWN_INFO_1M (BL_SF_SIZE_1M - BL_SF_DWN_INFO_SIZE)
#define BL_SF_DWN_INFO_MV28_BB 0x0007FF00
#define BL_SF_LAST_PAGE_START_ADDR_4M 0x17F00
#define BL_SF_LAST_PAGE_START_ADDR_64K 0xDF00
#define BL_SF_LAST_PAGE_START_ADDR_1M 0xFF00
#define BL_BR_9600 440
#define BL_BR_19200 220
#define BL_BR_38400 110
#define BL_BR_57600 73
// Configuration Register Definition
#define BL_CFG_BIT_0 0x01
#define BL_CFG_BIT_1 0x02
#define BL_CFG_BIT_2 0x04
#define BL_CFG_BIT_3 0x08
#define BL_CFG_BIT_4 0x10
#define BL_TMR_100ms 100
#define BL_TMR_500ms 500
#define BL_TMR_1s 1000
#define BL_TIMEOUT_ON_BSPI_RDID 0x00000001
#define BL_TIMEOUT_ON_BSPI_RDSR 0x00000002
#define BL_TIMEOUT_ON_BSPI_WREN 0x00000004
#define BL_TIMEOUT_ON_BSPI_BULK_ERASE 0x00000008
#define BL_TIMEOUT_ON_BSPI_PP 0x00000010
#define BL_TIMEOUT_ON_SF_READ 0x00000020
#define BL_MON0 0x20
#define BL_STORE_IN_SF 0x00
#define BL_STORE_IN_RAM 0x01
// mem field of dwn_ctrl_flags : 2 bit field
#define BL_SDRAM 0x00
#define BL_EXPRAM 0x01
#define BL_RAM_A 0x02
#define SELECT_SDRAM 0x1
#define SELECT_BSPI 0x0
// CFG4 CFG3
// 0 0 -> BL_MODE_PATCH_UPDATE: Load Patch into Serial Flash
// 0 1 -> BL_MODE_NO_PATCH Patch not activated.
// 1 0 -> BL_MODE_LOAD_PATCH: Activate patch
// 1 1 -> (Not Used)
#define BL_MODE_PATCH_UPDATE 0x00
#define BL_MODE_NO_PATCH 0x01
#define BL_MODE_LOAD_PATCH 0x02
#define BL_MODE_LOAD_PATCH_FROM_I2C 0x03
#define BL_MODE_UPDATE_SF 0x01
#define BL_MODE_DWN_FROM_SF_2_EXPRAM 0x03
#define BL_MODE_DWN_FROM_SF_2_RAM_A 0x05
#define BL_MODE_EXECUTE_FROM_RAM_A 0x07
//#define TP_ON() PDA |= 0x00000020
//#define TP_OFF() PDA &= 0xFFFFFFDF
#define TP_ON() do{}while(0)
#define TP_OFF() do{}while(0)
// Definition for ctr_update transition
#define BL_PATCH_SDRAM_CHECKSUM_POS 0xFC
#define BL_PATCH_SDRAM_CODE_SIZE_POS 0xF8
#define BL_PATCH_SDRAM_MAX_ADDR_POS 0xF4
#define BL_PATCH_CODE_CHECKSUM_POS 0xF0
#define BL_PATCH_CODE_SIZE_POS 0xEC
#define BL_PATCH_MAX_ADDR_POS 0xE8
#define BL_MV28_CHECKSUM 0xFC
#define BL_MV28_CODE_SIZE 0xF8
#define BL_MV28_MAX_ADDR 0xF4
#define BL_FROM_SF 0x00
#define BL_FROM_I2C 0x01
#define BL_I2C_SLAVE_ADDRESS 0xE0
#define BL_I2C_MSG_LEN 0x00
#define BL_I2C_OP_CODE 0x01
#define BL_I2C_START_ADDRESS 0x11
#define BL_I2C_DATA_MSG 0x22
#define BL_I2C_RUN 0x33
#define BL_I2C_INFO 0x44
#define BL_I2C_RUN_ROM_CODE 0x55
#define BL_I2C_XFER_ON 0x66
#define BL_I2C_XFER_OFF 0x77
#define BL_I2C_EMERGENCY_INIT 0xEE
#define BL_I2C_MSG_FIRST_BYTE 0x02
#define BL_I2C_ACK_LEN 0x02
#define BL_RAM_A_INFO 0x00
#define BL_SDRAM_INFO 0x01
#define BL_RAM_A_INFO_LEN 0x0D
#define BL_SDRAM_INFO_LEN 0x0D
/* Default size of Link Layer frame, can be lowered by HostIF command */
#define BL_I2C_CRQ_OR_MASK 0x0002 // use to set the CRQ high (inactive)
#define BL_I2C_CRQ_AND_MASK 0xFFFD // use to set the CRQ low (active)
#define BL_I2C_BUSY() (PDB |= BL_I2C_CRQ_OR_MASK)
#define BL_I2C_READY() (PDB &= BL_I2C_CRQ_AND_MASK)
#endif /* _BLGENDEF_H */
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