blmain.c

本程序为ST公司开发的源代码

/**************************************************
 *
 * blmain.c
 *
 * CVS ID:   $Id: blmain.c,v 1.17 2007/10/22 10:14:33 marcucci Exp $
 * Author:   Maurizio Marcucci [MM] - STM
 * Date:     $Date: 2007/10/22 10:14:33 $
 * Revision: $Revision: 1.17 $
 * 
 * Description:
 * 
 *
 ***************************************************
 * 
 * COPYRIGHT (C) ST Microelectronics  2005
 *            All Rights Reserved
 *
 ***************************************************
 *
 * STM CVS Log:
 *
 * $Log: blmain.c,v $
 * Revision 1.17  2007/10/22 10:14:33  marcucci
 * SF selection on CFG1 intead of CFG0 to allow CD only application
 *
 * Revision 1.16  2007/09/19 11:29:19  marcucci
 * GPIOs set as input only in case of code ROM Code
 *
 * Revision 1.15  2007/09/10 09:21:55  marcucci
 * All GPIO's set as input by S/W
 *
 * Revision 1.14  2007/07/13 11:05:03  marcucci
 * Initilaize BSPI only when it is necessary
 *
 * Revision 1.13  2007/07/02 08:41:18  marcucci
 * I2C Bootloader
 *
 * Revision 1.12  2007/02/15 13:09:48  marcucci
 * Bootloader Optimization
 *
 * Revision 1.11  2006/10/23 09:00:25  marcucci
 * Functions for Mirror Jump are execute in ARM mode
 *
 * Revision 1.10  2006/09/18 09:55:20  belardi
 * Corrected CVS keyword usage
 *
 * Revision 1.9  2006/09/18 09:22:15  belardi
 * Added Log CVS keyword into file header
 *
 *
 ***************************************************/
#include "configuration.h"

#include "blgendef.h"
#include "blmsgdef.h"
#include "hwreg.h"
#include "memutil.h"




void bl_pcintf(void);
void bl_pcint_init(void);
void bl_i2c_init(void);
void bl_bspi_init(BL_BSPI_STRUCT *bl_bspi_ptr);
void Reset_Handler(uint32 PATCH_TABLE_ADDRESS);
void rccu_init(void);
void bl_read_patch_code_info(BL_BSPI_STRUCT *bl_bspi_ptr);
void bl_CopyProgram2Sdram(uint32 size, BL_BSPI_STRUCT *bl_bspi_ptr);
void bl_WakeUpBSPI(BL_BSPI_STRUCT *bl_bspi_ptr);
void bl_copy_jt(void);
uint32 bl_CopyPatchedCode(BL_BSPI_STRUCT *bl_bspi_ptr);
extern void bl_i2cif(void);
extern void configure_gpio(unsigned int port, unsigned int bit, unsigned int function);

// The Boot Loader Variables are fixed at RAM_B starting address.
// The room occupied by Bootloader variables can be re-used by MASK ROM
// Software.
BL_STRUCT * const bl = 
{
  (BL_STRUCT *) 0x60000000
};



void bl_hw_init(void)
{
 
 rccu_init();
 

 //Switch-on  SYNC_APB Peripherals

 SAB_PCG0.field.bridge = 1; // Bit 0   0x0001
 SAB_PCG0.field.wui = 0;    // Bit 1   0x0002
 SAB_PCG0.field.dmac = 0;   // Bit 2   0x0004 
 SAB_PCG0.field.rccu = 1;   // Bit 3   0x0008
 SAB_PCG0.field.bspi = 1;   // Bit 4   0x0010
 SAB_PCG0.field.uart0 = 1;  // Bit 5   0x0020
 SAB_PCG0.field.uart1 = 1;  // Bit 6   0x0040
 SAB_PCG0.field.eft0 = 0;   // Bit 7   0x0080
 SAB_PCG0.field.eft1 = 0;   // Bit 8   0x0100
 SAB_PCG0.field.sdramc = 0; // Bit 9   0x0200
 SAB_PCG0.field.gcr = 1;    // Bit 10  0x0400
 SAB_PCG0.field.gpioa = 1;  // Bit 11  0x0800
 SAB_PCG0.field.gpiob = 1;  // Bit 12  0x1000
 SAB_PCG0.field.i2c = 1;    // Bit 13  0x2000
 
 SAB_PUR0.field.bridge = 1; // Bit 0   0x0001
 SAB_PUR0.field.wui = 0;    // Bit 1   0x0002
 SAB_PUR0.field.dmac = 0;   // Bit 2   0x0004 
 SAB_PUR0.field.rccu = 1;   // Bit 3   0x0008
 SAB_PUR0.field.bspi = 1;   // Bit 4   0x0010
 SAB_PUR0.field.uart0 = 1;  // Bit 5   0x0020
 SAB_PUR0.field.uart1 = 1;  // Bit 6   0x0040
 SAB_PUR0.field.eft0 = 0;   // Bit 7   0x0080
 SAB_PUR0.field.eft1 = 0;   // Bit 8   0x0100
 SAB_PUR0.field.sdramc = 0; // Bit 9   0x0200
 SAB_PUR0.field.gcr = 1;    // Bit 10  0x0400
 SAB_PUR0.field.gpioa = 1;  // Bit 11  0x0800
 SAB_PUR0.field.gpiob = 1;  // Bit 12  0x1000
 SAB_PUR0.field.i2c = 1;    // Bit 13  0x2000


 //SAB_EMPCG0.field.bspi = 0;

 //Switch-on  ASYNC APB Peripherals
 AAB_PCG0.field.bridge = 1;    // Bit 0
 AAB_PCG0.field.wdg = 0;       // Bit 1
 AAB_PCG0.field.dsp = 0;       // Bit 2
 AAB_PCG0.field.dec = 0;       // Bit 3
 AAB_PCG0.field.circ_clv = 0;  // Bit 4
 AAB_PCG0.field.afe = 0;       // Bit 5
 AAB_PCG0.field.acq = 0;       // Bit 6
 AAB_PCG0.field.oif = 0;       // Bit 7
 AAB_PCG0.field.block_dec = 0; // Bit 8
 

 AAB_PUR0.field.bridge = 1;    // Bit 0
 AAB_PUR0.field.wdg = 0;       // Bit 1
 AAB_PUR0.field.dsp = 0;       // Bit 2
 AAB_PUR0.field.dec = 0;       // Bit 3
 AAB_PUR0.field.circ_clv = 0;  // Bit 4
 AAB_PUR0.field.afe = 0;       // Bit 5
 AAB_PUR0.field.acq = 0;       // Bit 6
 AAB_PUR0.field.oif = 0;       // Bit 7
 AAB_PUR0.field.block_dec = 0; // Bit 8


 //Switch-on  SYNC AHB Peripherals

 CGC_PCG1.field.eic = 1;
 CGC_PCG1.field.dmac = 0;
 CGC_PCG1.field.sdramc = 0;
 CGC_PCG1.field.exp_ram = 1; 
 
 CGC_PCG1.field.ch_itf = 0;
 CGC_PCG1.field.src = 0;
 CGC_PCG1.field.usb = 0;
 CGC_PCG1.field.input_port = 0; 

 CGC_PUR1.field.eic = 1;
 CGC_PUR1.field.dmac = 0;
 CGC_PUR1.field.sdramc = 0;
 
 CGC_PUR1.field.exp_ram = 1; // Only if MV28 is used 
 
 CGC_PUR1.field.ch_itf = 0;
 CGC_PUR1.field.src = 0;
 CGC_PUR1.field.usb = 0;
 CGC_PUR1.field.input_port = 0; 


 //configure_gpio(BL_PORT_A, BL_GPIO_0, BL_GPIO_IN);  // 
 //configure_gpio(BL_PORT_A, BL_GPIO_1, BL_GPIO_IN);  // 
 //configure_gpio(BL_PORT_A, BL_GPIO_2, BL_GPIO_IN);  // 
 //configure_gpio(BL_PORT_A, BL_GPIO_3, BL_GPIO_IN);  // 
 //configure_gpio(BL_PORT_A, BL_GPIO_4, BL_GPIO_IN);  // 
 //configure_gpio(BL_PORT_A, BL_GPIO_5, BL_GPIO_OUT_PP);  // MON_0 
 //configure_gpio(BL_PORT_A, BL_GPIO_6, BL_GPIO_IN);  // 
 //configure_gpio(BL_PORT_A, BL_GPIO_7, BL_GPIO_IN);  // 
 //configure_gpio(BL_PORT_A, BL_GPIO_8, BL_GPIO_IN); // Home Switch 


 //configure_gpio(BL_PORT_B, BL_GPIO_0, BL_GPIO_OUT_PP); // SFLASH_SS
 //configure_gpio(BL_PORT_B, BL_GPIO_1, BL_GPIO_IN);      
 //configure_gpio(BL_PORT_B, BL_GPIO_2, BL_GPIO_IN ); 
 //configure_gpio(BL_PORT_B, BL_GPIO_3, BL_GPIO_IN ); 
 //configure_gpio(BL_PORT_B, BL_GPIO_4, BL_GPIO_IN);  // TX UART0
 //configure_gpio(BL_PORT_B, BL_GPIO_5, BL_GPIO_IN); 
 //configure_gpio(BL_PORT_B, BL_GPIO_6, BL_GPIO_IN);  // TX UART1
 //configure_gpio(BL_PORT_B, BL_GPIO_7, BL_GPIO_IN); 
 //configure_gpio(BL_PORT_B, BL_GPIO_8, BL_GPIO_IN); 
 

 #if (1 == USE_BOOTLOADER_PATCH_MODE)
 //Set All Gpio as input port
 PC0A = 0x3FFF;
 PC1A = 0x0000;
 PC2A = 0x0000;
  
 PC0B = 0xFFFF;
 PC1B = 0x0000;
 PC2B = 0x0000;
 #endif
  
 GCR1.field.sdram_sel = 0;  // Select BSPI Bus on SDRAM Shared Pads
 GCR1.field.usb_pad_en = 0; // Because UART1 pin are Alternate Function of USB pin
                            // make sure that USB pins are disabled

 EIC_ICR.field.irq_en = 0;
 EIC_IER = 0x00000000;
} 
 

void bootloader(void)
{  
  //TP_ON();
  // BSPI Bus on SDRAM lines
  // SDRAM not activated.
  bl_hw_init();
  //bl_InterruptEnable();  
 
  // Interrupt Enable
  GCR1.field.eic_sres = 1;
  GCR1.field.eic_sres = 0;
 
  EIC_ICR.field.irq_en = 1; 
  // Interrupt Enable

  //bl_pcint_init(); // USING UART 1
  //bl_bspi_init(&bl->bspi);  
    
  bl->conf_pin_status = GCR2.field.cfg;
  bl->dwn_ctrl_flags.sf_type = (bl->conf_pin_status & BL_CFG_BIT_1) >> 1;
  bl->conf_pin_status &= (BL_CFG_BIT_4 | BL_CFG_BIT_3);
  bl->conf_pin_status >>= 3;
  //bl->dwn_mode = BL_RAM_A;
  //bl->dwn_ctrl_flags.sdram_connected = 1;
  bl->dwn_ctrl_flags.patch_code_activated = 0;
  
  // Setting for MV28 Mode
  //bl->dwn_ctrl_flags.mem = BL_EXPRAM;
  
#if (0 == USE_BOOTLOADER_PATCH_MODE)
  bl->conf_pin_status = BL_MODE_NO_PATCH;
#endif

 //#ifdef BL_BOOT_MV28_TEST
 // bl->conf_pin_status |= 1;
 //#endif 
  
 // 4Mbit Serial Flash
  bl->patch_area_size = BL_PATCH_AREA_SIZE_4M;
  bl->sf_data_4_sdram_size = BL_SF_DATA_4_SDRAM_SIZE_4M;
  bl->sf_overlay_area_start_addr = BL_SF_OVERLAY_AREA_START_ADDR_4M;
  bl->sf_dwn_info = BL_SF_DWN_INFO_4M;
  if(bl->dwn_ctrl_flags.sf_type == BL_MP25P05)
  {
    //1Mbit Kbit Serial Flash
    bl->patch_area_size = BL_PATCH_AREA_SIZE_1M;
    bl->sf_data_4_sdram_size = BL_SF_DATA_4_SDRAM_SIZE_1M;
    bl->sf_overlay_area_start_addr = BL_SF_OVERLAY_AREA_START_ADDR_1M;
    bl->sf_dwn_info = BL_SF_DWN_INFO_1M;
  }
   
  if(bl->conf_pin_status == BL_MODE_LOAD_PATCH_FROM_I2C)
  {
   bl_i2c_init();
   //BL_I2C_READY();
  // Boot From IIC.
   while(1)
   {
    bl_i2cif();
   }    
  }
  else
  {
   bl_bspi_init(&bl->bspi);  
   
   if(bl->conf_pin_status == BL_MODE_NO_PATCH)
   {
    // In this state No serial Flash is needed.
    // Just go to the Mask ROM S/W.   
    bl_copy_jt();

    sdram_init(0x40000000);

    // Disable Interrupt: CPSR ?
    EIC_ICR.field.irq_en = 0;
    Reset_Handler(0x40000000);
   }

   
   if(bl->conf_pin_status == BL_MODE_LOAD_PATCH)
   {
    // Load Patch Code from Serial Flash and activate it
   
    bl->code_checksum = 0;
   
    bl_WakeUpBSPI(&bl->bspi);
   
    bl_read_patch_code_info(&bl->bspi);
   
    bl_CopyPatchedCode(&bl->bspi);
    if(bl->code_checksum == bl->sf_code_checksum.all)
    {
     // Initialize SDRAM
     sdram_init(0x40000000);
     
     // Load Patch Code into SDRAM only if it is.
     if(bl->sf_sdram_code_size.all)
     {      
      bl->code_checksum = 0;
      bl_CopyProgram2Sdram(bl->sf_sdram_max_addr.all, &bl->bspi);	
      if(bl->code_checksum == bl->sf_sdram_code_checksum.all)
      {
       Reset_Handler(0x40000000); 	
      }
     }
     else
     {
      Reset_Handler(0x40000000); 		
     }
    }
    // If Checsum Fails Go to Pc Interface Environment
    // To debug.
    bl_pcint_init(); // USING UART 1
   // Update Patch Code.
    while(1)
    {
     bl_pcintf();   
    }
   }
   
  
   //if(bl->conf_pin_status == BL_MODE_PATCH_UPDATE)
   //{
    bl_pcint_init(); // USING UART 1
    // Update Patch Code.
    while(1)
    {
     bl_pcintf();   
    }  
   //} 
  } 
 }
//*****************************End of blmain.c********************************/