bkdhdl.c

本程序为ST公司开发的源代码

/******************************************************************************
 *
 * bkdhdl.c
 *
 * CVS ID:   $Id: bkdhdl.c,v 1.40 2007/03/16 07:17:37 hara Exp $
 * Author:   Filippo Brenna [FB] - STM
 * Date:     $Date: 2007/03/16 07:17:37 $
 * Revision: $Revision: 1.40 $
 *
 * Description:
 *
 *   block decoder and dma handler
 *
 ******************************************************************************
 *
 * COPYRIGHT (C) ST Microelectronics  2005
 *            All Rights Reserved
 *
 ******************************************************************************
 *
 * STM CVS Log:
 *
 * $Log: bkdhdl.c,v $
 * Revision 1.40  2007/03/16 07:17:37  hara
 * Enable secure subcode mode for CDDA
 *
 * Revision 1.39  2006/10/10 12:00:01  belardi
 * Merge of m8_cav2_cm80507
 * - renamed function
 *
 * Revision 1.38  2006/09/18 09:55:20  belardi
 * Corrected CVS keyword usage
 *
 * Revision 1.37  2006/09/18 09:22:23  belardi
 * Added Log CVS keyword into file header
 *
 * Revision 1.36  2006/09/15 20:15:05  belardi
 * Added Log CVS keyword into file header
 *
 *
 ******************************************************************************/

#include "gendef.h"
#include "osal.h"
#include "srvinc.h"
#include "hwreg.h"
#include "bkdhdl.h"
#include "capture.h"
#include "utility.h"
#include "debug.h"


/******************************************************************************/
/* BD vars                                                                  */
/******************************************************************************/

t_lba bd_start_lba;
t_lba bd_stop_lba;
t_bd_params bd_params;
uint16 dma_ch1_rx_block_idx;
uint8 bd_sw_sts;


/******************************************************************************/
/* Function:  bd_dma_init                                                     */
/*                                                                            */
/*! \brief    init for block decoder and dma
 *  \param
 *  \return
 *  \remark
 */
/******************************************************************************/

void bd_dma_init(t_bd_params *bd_params)
{
  uint8 *esp_input_buffer = bd_params->esp_params.input_buffer;

  bd_sw_sts = BD_XFER_IDLE;

  /* Audio data */
  BD_CTL1.field.secure_mode = 0;
//  BD_CTL1.field.secure_subcode = 0;
  BD_CTL1.field.secure_subcode = 1;     /* Avoid no meaning LBA error by Subcode Mode 2 [FH] 16/Mar/2007 */ 
  BD_CTL1.field.secure_sync = 1;
  BD_CTL1.field.auto_xa = 0;

  BD_CTL2.field.block_size = 2;         /* 3.0 kb */
  if (bd_params->esp)
  {
    BD_CTL2.field.tbr_max = 3;          /* Max 14 suspicious sectors */
  }
  else
  {
    BD_CTL2.field.tbr_max = 0;          /* Max 2 suspicious sectors */
  }

  BD_CTL2.field.send_links = 0;
  BD_CTL2.field.packet_disc = 0;
  BD_CTL2.field.fw_stop = 0;
  BD_CTL2.field.fw_start = 0;


  BD_TX_CTL.field.data_type = bd_params->data_type;


  BD_TX_CTL.field.auto_data = 0;       /* Enable auto CD_ROM/CDDA detection */
  BD_TX_CTL.field.auto_mode = 0;       /* Enable auto CD_ROM Detection */
  BD_TX_CTL.field.auto_form = 0;
  BD_TX_CTL.field.secure_form = 0;

  if (DATA_TYPE_CDDA == bd_params->data_type) /* cdda */
  {
    if (bd_params->esp)
    {
      BD_ERR_CTL.field.allow_all_errors = 0;
    }
    else
    {
      BD_ERR_CTL.field.allow_all_errors = 1;  /* No ESP buffer, No retry to capture */
    }
  }
  else
  {
    BD_ERR_CTL.field.allow_all_errors = 0;
  }

  BD_ERR_CTL.field.type_check = 0; //[OK] 07/Sep/06 changed from 1
  BD_ERR_CTL.field.ecc_check = 1;
  BD_ERR_CTL.field.c3_check = 1;
  BD_ERR_CTL.field.edc_check = 1;

  BD_C3_CTL1.field.dbl_err_cor = 1;
  BD_C3_CTL1.field.try_sng_err = 1;
  BD_C3_CTL1.field.cor_til_noflag = 1;
  BD_C3_CTL1.field.cor_til_noerr = 1;
  BD_C3_CTL1.field.max_c2_flags = 7;

  BD_C3_CTL2.field.max_pass = 0x0F;
  BD_C3_CTL2.field.no_ecc_edc_ok = 0;
  BD_C3_CTL2.field.no_ecc = 0;

  /* at the beginning START_LBA must be 0 */
  BD_START_LBA_H = 0xFF;
  BD_START_LBA_M = 0xFF;
  BD_START_LBA_L = 0xFF;
  /* at the beginning STOP_LBA must be 0 */
  BD_STOP_LBA_H = 0xFF;
  BD_STOP_LBA_M = 0xFF;
  BD_STOP_LBA_L = 0xFF;


  /* tdb */
  BD_TOP_BLK_H = 0x01;
  BD_TOP_BLK_L = 0xFE;

  BD_IT_CTL.field.start_it_en = 0;
  BD_IT_CTL.field.stop_it_en = 0;
  BD_IT_CTL.field.blk_it_en = 0;

  DF_CTL_REG.field.input_block_layout = 1;       /* 3.0 kb according to BD_CTL2.field.block_size = 1;  3.0 kb */

  if (DATA_TYPE_CDDA == bd_params->data_type)
  {
    DF_CTL_REG.field.output_block_size = 1;  /* 0 = 2352, 1=2560, 2=2856 */
  }
  else /* if(DATA_TYPE_CDDA != bd_params->data_type) */
  {
    DF_CTL_REG.field.output_block_size = 0;  /* 0 = 2352, 1=2560, 2=2856 */
  }


  DF_CTL_REG.field.interleave = 0;

  DF_TOP_BLOCK = 0xFF;

#if (1 == HAVE_SHOCK_MEMORY)
  if (ADPCM_ON == cap_config.adpcm)
  {
    if (DATA_TYPE_CDDA == bd_params->data_type) /* cdda */
    {
      OIF_SP_CTRL.field.en_compress = 1;
      OIF_SOFT_RST.field.adpcm_enc_rst = 0;
      OIF_SOFT_RST.field.adpcm_dec_rst = 0;

      DF_CTL_REG.field.interleave = 1;
    }
    else
    {
      OIF_SP_CTRL.field.en_compress = 0;
      OIF_SOFT_RST.field.adpcm_enc_rst = 1;
      OIF_SOFT_RST.field.adpcm_dec_rst = 1;
      DF_CTL_REG.field.interleave = 0;
    }
  }
  else
#endif
  {
    OIF_SP_CTRL.field.en_compress = 0;
    DF_CTL_REG.field.interleave = 0;
  }


  DMA_CTRL1.field.enable = 0; /* Disable DMA Ch 1 */

  OSAL_isr_install(OSAL_ISR_DMA1, 0x0f, dma_ch1_isr_irq);

  SetDMAChannel(DMA_CH1, CHITF_RD_CH);

  if (DATA_TYPE_CDDA != bd_params->data_type) /* CDROM */
  {
    SetUpDMA(DMA_CH1, (uint32 *) &CIF_RDDATA, /* Source Address */
                (uint32 *) esp_input_buffer, /* Destination */
                DMA_WORD_SIZE_IS_WORD, DMA_WORD_SIZE_IS_WORD, 2352,
             /* according to DF_CTL_REG.field.output_block_size = 0; 0 = 2352, 1=2560, 3=2856 */
                DMA_BURST_IS_8_WORD,
             /* according to CIF_CONF.field.rd_burst_len = 2; dim half fifo size */
                DMA_NO_INCREMENT, /* Source Increment */
                DMA_INCREMENT, /* Destination Increment */
                DMA_PERIPHERAL_IS_THE_SOURCE, 0);
  }
  else /* CDDA */
  {
#if (1 == HAVE_SHOCK_MEMORY)
    if (ADPCM_ON == cap_config.adpcm)
    {
      SetUpDMA(DMA_CH1, (uint32 *) &CIF_RDDATA, /* Source Address */
                (uint32 *) esp_input_buffer, /* Destination */
                DMA_WORD_SIZE_IS_WORD, DMA_WORD_SIZE_IS_WORD, 924, /* */
                DMA_BURST_IS_8_WORD,
               /* according to CIF_CONF.field.rd_burst_len = 2; dim half fifo size */
                DMA_NO_INCREMENT, /* Source Increment */
                DMA_INCREMENT, /* Destination Increment */
                DMA_PERIPHERAL_IS_THE_SOURCE, 0);
    }
    else
#endif
    {
      SetUpDMA(DMA_CH1, (uint32 *) &CIF_RDDATA, /* Source Address */
                (uint32 *) esp_input_buffer, /* Destination */
                DMA_WORD_SIZE_IS_WORD, DMA_WORD_SIZE_IS_WORD, 2560,
               /* according to DF_CTL_REG.field.output_block_size = 0; 0 = 2352, 1=2560, 3=2856 */
                DMA_BURST_IS_8_WORD,
               /* according to CIF_CONF.field.rd_burst_len = 2; dim half fifo size */
                DMA_NO_INCREMENT, /* Source Increment */
                DMA_INCREMENT, /* Destination Increment */
                DMA_PERIPHERAL_IS_THE_SOURCE, 0);
    }
  }

  DMA_MASK.field.sim1 = 1; /* Interrupt On Xfer End */
  DMA_MASK.field.sem1 = 1; /* Interrupt On Xfer Error */

  DMA_CLR.field.sic1 = 1;
  DMA_CLR.field.sec1 = 1;


  CIF_CONF.field.rd_fifo_rst = 1;
  /* Read Burst Length */
  /* 0 -> 1  Word */
  /* 1 -> 4  Word */
  /* 2 -> 8  Word */
  /* 3 -> 16 Word */
  CIF_CONF.field.rd_burst_len = 2;
  CIF_CONF.field.rd_en = 1;

  OSAL_isr_install(OSAL_ISR_DMA, 0x0f, dma_ch3_isr_irq);
  OSAL_isr_install(OSAL_ISR_BD, 0x0f, bd_isr_irq);
}

/******************************************************************************/
/* Function:  bd_isr_irq                                                      */
/*                                                                            */
/*! \brief    block decoder isr
 *  \param
 *  \return
 *  \remark
 */
/******************************************************************************/

void bd_isr_irq(void)
{
  BD_STS_UNION bd_sts;
  t_bd_event *pout_bd_event;

  bd_sts = BD_STS;
  pout_bd_event = (t_bd_event *) pevent_get_out(BD_IRQ_EVENT);

  /* BD_XFER_IDLE */
  if (BD_XFER_IDLE == bd_sw_sts)
  {
    if (bd_sts.field.end_of_xfer)
    {
      if (0 == bd_sts.field.xfer)
      {
        /* overshoot detection */
        pout_bd_event->status = CAP_BD_SECTOR_IT;
      }
      else
      {
        /* start lba found */
        pout_bd_event->status = RUNNING;
        DF_LAST_BLOCK = 0x00;
        DF_LAST_V_BLOCK = 0x00;

        bd_sw_sts = BD_XFER_ACTIVE;
      }
      event_set_out(BD_IRQ_EVENT);
    }
  }

  /* BD_XFER_ACTIVE */
  if (BD_XFER_ACTIVE == bd_sw_sts)
  {
    if ((0 == bd_sts.field.xfer) && bd_sts.field.end_of_xfer)
    {
      /* stop lba found or error */
      if (bd_sts.field.error_code)
      {
        pout_bd_event->status = CAP_BD_ERROR | bd_sts.field.error_code;
      }
      else
      {
        pout_bd_event->status = READY;
      }

      pout_bd_event->last_good_lba = ((BD_START_LBA_H << 16)
                                        | (BD_START_LBA_M << 8)
                                        | BD_START_LBA_L);
      pout_bd_event->last_good_lba += 150;

      pout_bd_event->last_block_cnt = DF_LAST_BLOCK;
      pout_bd_event->last_valid_block_cnt = DF_LAST_V_BLOCK;
      event_set_out(BD_IRQ_EVENT);

      BD_START_LBA_H = 0xFF;
      BD_START_LBA_M = 0xFF;
      BD_START_LBA_L = 0xFF;

      bd_sw_sts = BD_XFER_IDLE;
    }
  }

  event_disable_scheduling();
  event_out_shedule(BD_IRQ_EVENT);
  event_enable_scheduling();
}


#define ESP_INPUT_BUFFER          bd_params.esp_params.input_buffer
#define ESP_INPUT_BUFFER_SIZE     bd_params.esp_params.input_buffer_size
#define ESP_WARNING_OVERFLOW_THRS bd_params.esp_params.warning_overflow_thrs
#define ESP_INPUT_SECTOR_SIZE     cap_config.esp_params.input_sector_size

/******************************************************************************/
/* Function:  dma_ch1_isr_irq                                                 */
/*                                                                            */
/*! \brief    DMA interrupt handler
 *  \param    void
 *  \return   void
 *  \remark
 */
/******************************************************************************/

void dma_ch1_isr_irq(void)
{
  DMA_STATUS_UNION dma_status;
  uint8 *esp_input_buffer;

  dma_status = DMA_STATUS;

  if (dma_status.all)
  {
    if (dma_status.field.int1)
    {
      DMA_CLR.field.sic1 = 1;

      if ((ESP_INPUT_BUFFER_SIZE - 1) == dma_ch1_rx_block_idx)
      {
        dma_ch1_rx_block_idx = 0;
      }
      else
      {
        dma_ch1_rx_block_idx++;
      }
      cap_esp_write_controller_update_isr();

      esp_input_buffer = ESP_INPUT_BUFFER + (dma_ch1_rx_block_idx * ESP_INPUT_SECTOR_SIZE);
      DMA_DEST_LO1 = (uint32) esp_input_buffer;
      DMA_DEST_HI1 = (uint32) (esp_input_buffer) >> 16;

      DMA_CTRL1.field.enable = 1;
      event_set_dma_write(READY);
    }

    if (dma_status.field.err1)
    {
      DMA_CLR.field.sec1 = 1;
      event_set_dma_write(CAP_DMA1_XFER_ERROR_EVENT);
    }

    event_disable_scheduling();
    event_out_shedule(DMA_IRQ_WRITE_EVENT);
    event_enable_scheduling();
  }
}


/******************************************************************************/
/* Function:  dma_ch3_isr_irq                                                 */
/*                                                                            */
/*! \brief    DMA interrupt handler
 *  \param    void
 *  \return   void
 *  \remark
 */
/******************************************************************************/

void dma_ch3_isr_irq(void)
{
  DMA_STATUS_UNION dma_status;

  dma_status = DMA_STATUS;

  if (dma_status.all)
  {
    if (dma_status.field.int3)
    {
      DMA_CLR.field.sic3 = 1;
      event_set_dma_xfer(READY);
    }

    if (dma_status.field.err3)
    {
      DMA_CLR.field.sec3 = 1;
      event_set_dma_xfer(CAP_DMA3_XFER_ERROR_EVENT);
    }

    event_disable_scheduling();
    event_out_shedule(DMA_IRQ_XFER_EVENT);
    event_enable_scheduling();
  }
}

/******************************************************************************
*******************************************************************************/