bspidef.h

本程序为ST公司开发的源代码

/**************************************************
 *
 *
 * CVS ID:   $Id: bspidef.h,v 1.1 2006/01/31 18:50:14 belardi Exp $
 * Author:   Maurizio Marcucci [MM] - STM
 * Date:     $Date: 2006/01/31 18:50:14 $
 * Revision: $Revision: 1.1 $
 * 
 * Description:
 * 
 *   Accordo+ Hardware registers definition
 *
 ***************************************************
 * 
 * COPYRIGHT (C) ST Microelectronics  2005
 *            All Rights Reserved
 *
 ***************************************************/
// BSPI_CSR1

typedef struct
{
 UInt bspe         :1;   // Bit 0
 UInt mstr         :1;   // Bit 1
 UInt rie          :2;   // Bit 2-3
 UInt reie         :1;   // Bit 4
 UInt              :2;   // Bit 5-6
 UInt beie         :1;   // Bit 7
 UInt cpol         :1;   // Bit 8
 UInt cpha         :1;   // Bit 9
 UInt wl           :2;   // Bit 10-11
 UInt rfs          :4;   // Bit 12-15
 UInt              :16;
} BSPI_CSR1_STRUCT;


typedef union
{
 BSPI_CSR1_STRUCT field;
 uint32 all;
} BSPI_CSR1_UNION;


// BSPI_CSR2

typedef struct
{
 UInt dfifo           :1;   // Bit 0
 UInt                 :1;   // Bit 1
 UInt berr            :1;   // Bit 2
 UInt rfne            :1;   // Bit 3
 UInt rff             :1;   // Bit 4
 UInt rofl            :1;   // Bit 5
 UInt tfe             :1;   // Bit 6
 UInt tufl            :1;   // Bit 7
 UInt tff             :1;   // Bit 8
 UInt tfne            :1;   // Bit 9
 UInt tfs             :4;   // Bit 10-13
 UInt tie             :2;   // Bit 14-15
 UInt                 :16;
} BSPI_CSR2_STRUCT;


typedef union
{
 BSPI_CSR2_STRUCT field;
 uint32 all;
} BSPI_CSR2_UNION;



typedef struct
{
 UInt mask_ss         :1;   // Bit 0
 UInt dma_en          :1;   // Bit 1
 UInt tburst_len      :2;   // Bit 2-3
 UInt rburst_len      :2;   // Bit 4-5
 UInt treq_len        :1;   // Bit 6
 UInt rreq_len        :1;   // Bit 7
 UInt                 :24;
} BSPI_CSR3_STRUCT;


typedef union
{
 BSPI_CSR3_STRUCT field;
 uint32 all;
} BSPI_CSR3_UNION;