sabdef.h

本程序为ST公司开发的源代码

/**************************************************
 *
 *
 * CVS ID:   $Id: sabdef.h,v 1.4 2006/05/29 20:05:13 belardi Exp $
 * Author:   Maurizio Marcucci [MM] - STM
 * Date:     $Date: 2006/05/29 20:05:13 $
 * Revision: $Revision: 1.4 $
 * 
 * Description:
 * 
 *   Accordo+ Hardware registers definition
 *
 ***************************************************
 * 
 * COPYRIGHT (C) ST Microelectronics  2005
 *            All Rights Reserved
 *
 ***************************************************/
// BSR Register
typedef struct
{
 UInt error: 1; // Bit 0
 UInt      : 3; // Bit 1-3
 UInt outm : 1; // Bit 4
 UInt      : 2; // Bit 5-6
 UInt pco  : 1; // Bit 7
 UInt pur  : 1; // Bit 8
 UInt      : 23;// Bit 9-31
} SAB_BSR_STRUCT;

typedef union
{
 SAB_BSR_STRUCT field;
 uint32     all;
} SAB_BSR_UNION;

// PAER

typedef struct
{
 UInt pa   : 24;
 UInt nRW  : 1;
 UInt      : 7;
} SAB_PAER_STRUCT;

typedef union
{
 SAB_PAER_STRUCT field;
 uint32      all;
}SAB_PAER_UNION;


// PCG0 register
// dma, rccu, gcr, sdramc blocks are working with the system Clock (HCLK) on AHB
// APB is necessary to access their program registers
// For these peripherals the corresponding bits of this register prevent ARM7TDI to access their address 
// range.


typedef struct
{
 UInt bridge : 1; // Bit 0   0x0001
 UInt wui    : 1; // Bit 1   0x0002
 UInt dmac   : 1; // Bit 2   0x0004 
 UInt rccu   : 1; // Bit 3   0x0008
 UInt bspi   : 1; // Bit 4   0x0010
 UInt uart0  : 1; // Bit 5   0x0020
 UInt uart1  : 1; // Bit 6   0x0040
 UInt eft0   : 1; // Bit 7   0x0080
 UInt eft1   : 1; // Bit 8   0x0100
 UInt sdramc : 1; // Bit 9   0x0200
 UInt gcr    : 1; // Bit 10  0x0400
 UInt gpioa  : 1; // Bit 11  0x0800
 UInt gpiob  : 1; // Bit 12  0x1000
 UInt i2c    : 1; // Bit 13  0x2000
 UInt        : 4;
 UInt bspi1  : 1; // Bit 18
 UInt        : 13;
} SAB_PER_BIT_STRUCT;

typedef union
{
 SAB_PER_BIT_STRUCT field;
 uint32      all;
} SAB_PER_BIT_UNION;