oifdef.h

本程序为ST公司开发的源代码

/**************************************************
 *
 *
 * CVS ID:   $Id: oifdef.h,v 1.5 2006/06/16 10:11:07 brenna Exp $
 * Author:   Maurizio Marcucci [MM] - STM
 * Date:     $Date: 2006/06/16 10:11:07 $
 * Revision: $Revision: 1.5 $
 * 
 * Description:
 * 
 *   Accordo+ Hardware registers definition
 *
 ***************************************************
 * 
 * COPYRIGHT (C) ST Microelectronics  2005
 *            All Rights Reserved
 *
 ***************************************************/
// OIF_DEF

/* INT_REASON register type definition */
typedef struct
{
  UInt  int_cdtext      : 1; // Bit 0
  UInt  int_misc_ap     : 1; // Bit 1
  UInt  int_ap	        : 1; // Bit 2
  UInt                  : 5; // Bit 3-7
  UInt                  : 24;
} OIF_INT_REASON_STRUCT;

typedef union
{
  uint32 all;
  OIF_INT_REASON_STRUCT field;
} OIF_INT_REASON_UNION;


/* SOFTWARE_RESET register type definition */
typedef struct
{
  UInt  i2s_ctrl        : 1; // Bit 0
  UInt  adpcm_blockend_rst : 1; // Bit 1
  UInt  spdif_ctrl      : 1; // Bit 2
  UInt  audio_equalizer : 1; // Bit 3
  UInt  adpcm_enc_rst   : 1; // Bit 4
  UInt  adpcm_dec_rst   : 1; // Bit 5  
  UInt  subcode_ctrl    : 1; // Bit 6
  UInt  audio_dac       : 1; // Bit 7
  UInt                  : 24;
} OIF_SOFT_RST_STRUCT;

typedef union
{
  uint32 all;
  OIF_SOFT_RST_STRUCT field;
} OIF_SOFT_RST_UNION;

/* AP_CONTROL_PART_1 regsiter type definition */
typedef struct
{
  UInt  current_data_shift  : 5; // Bit 0-4
  UInt  data_signed_ext     : 1; // Bit 5
  UInt  current_on_lock     : 1; // Bit 6
  UInt  audio_enable        : 1; // Bit 7
  UInt                      : 24;
} OIF_AP_CONTROL_PART_1_STRUCT;

typedef union
{
  uint32 all;
  OIF_AP_CONTROL_PART_1_STRUCT field;
} OIF_AP_CONTROL_PART_1_UNION;

/* AP_CONTROL_PART_2 register type definition */
typedef struct
{
  UInt  target_data_shift   : 5; // Bit 0-4
  UInt  enable_equalizer    : 1; // Bit 5
  UInt  enable_deemphasis   : 1; // Bit 6
  UInt  enable_sample_req   : 1; // Bit 7
  UInt                      : 24;
} OIF_AP_CONTROL_PART_2_STRUCT;

typedef union
{
  uint32 all;
  OIF_AP_CONTROL_PART_2_STRUCT field;
} OIF_AP_CONTROL_PART_2_UNION;

/* AP_STATUS register type definition */
typedef struct
{
  UInt  underflow_mode      : 2; // Bit 0-1
  UInt  int_undf            : 1; // Bit 2
  UInt  int_short_frame     : 1; // Bit 3
  UInt  int_long_frame      : 1; // Bit 4
  UInt  en_int_undf         : 1; // Bit 5
  UInt  en_int_short_frame  : 1; // Bit 6
  UInt  en_int_long_frame   : 1; // Bit 7
  UInt                      : 24;
} OIF_AP_STATUS_STRUCT;         

typedef union
{
  uint32 all;
  OIF_AP_STATUS_STRUCT field;
} OIF_AP_STATUS_UNION;

/* AP_EQUALIZER_CTRL register type definition */
typedef struct
{
  UInt  bass_boost    : 4; // Bit 0-3
  UInt  treble_boost  : 4; // Bit 4-7
  UInt                : 24;
} OIF_AP_EQUALIZER_CTRL_STRUCT;

typedef union
{
  uint32 all;
  OIF_AP_EQUALIZER_CTRL_STRUCT field;
} OIF_AP_EQUALIZER_CTRL_UNION;

/* AP_MUTE_CTRL register type definition */
typedef struct
{
  UInt  spdif_mute_md     : 2; // Bit 0-1
  UInt  spdif_force_mute  : 1; // Bit 2
  UInt  spdif_auto_mute   : 1; // Bit 3
  UInt  i2s_mute_md       : 2; // Bit 4-5
  UInt  i2s_force_mute    : 1; // Bit 6
  UInt  i2s_auto_mute     : 1; // Bit 7
  UInt                    : 24;
} OIF_AP_MUTE_CTRL_STRUCT;

typedef union
{
  uint32 all;
  OIF_AP_MUTE_CTRL_STRUCT field;
} OIF_AP_MUTE_CTRL_UNION;


// OIF_I2S_SPDIF_REG_0
// OIF_SPDIF_CHANNEL_STATUS
// OIF_I2S_CONTROL

/* I2S_CONTROL register type definition */
typedef struct
{
  UInt  slsi_pi2s       : 1; // Bit 0
  UInt  framelength     : 2; // Bit 1-2
  UInt  sclk_level      : 1; // Bit 3
  UInt  wclk_level      : 1; // Bit 4
  UInt  c2flags_level   : 1; // Bit 5
  UInt  sdata_level     : 1; // Bit 6
  UInt  audio_dac_clk   : 1; // Bit 7
  UInt                  : 24;
} OIF_I2S_OUTPUT_CONTROL_STRUCT;

typedef struct
{
  UInt  channel_status_left   : 4;
  UInt  channel_status_right  : 4;
  UInt                        : 24;
} OIF_SPDIF_CHANNEL_STATUS_STRUCT;

typedef union
{
  uint32 all;
  OIF_SPDIF_CHANNEL_STATUS_STRUCT mux_0_field;
  OIF_I2S_OUTPUT_CONTROL_STRUCT mux_1_field;
} OIF_I2S_SPDIF_REG_0_UNION;

/* SPDIF_CONTROL register type definition */
typedef struct
{
  UInt  spdif_data_mode : 3; // Bit 0-2
  UInt  spdif_efm_mode  : 1; // Bit 3
  UInt  validity_mux    : 1; // Bit 4
  UInt  v_st7           : 1; // Bit 5
  UInt  parity_level    : 1; // Bit 6
  UInt  i2s_spdif_mux   : 1; // Bit 7
  UInt                  : 24;
} OIF_SPDIF_CONTROL_STRUCT;

typedef union
{
  uint32 all;
  OIF_SPDIF_CONTROL_STRUCT field;
} OIF_SPDIF_CONTROL_UNION;


// OIF_I2S_SPDIF_REG_1
// OIF_I2S_DATA_FORMAT
// OIF_CLOCK_DEF_PART_1
typedef struct
{
  UInt  spdif_ratio           : 5; // Bit 0-4
  UInt  input_clock_selection : 2; // Bit 5-6
  UInt  invert_clock          : 1; // Bit 7
  UInt                        : 24;
} OIF_CLOCK_DEF_PART_1_STRUCT;

/* I2S_DATA_FORMAT register type definition */
typedef struct
{
  UInt  i2s_data_out_format : 4; // Bit 0-3
  UInt  i2s_data_in_format  : 4; // Bit 4-7
  UInt                      : 24;
} OIF_I2S_DATA_FORMAT_STRUCT;

typedef union
{
  uint32 all;
  OIF_I2S_DATA_FORMAT_STRUCT mux_1_field;
  OIF_CLOCK_DEF_PART_1_STRUCT mux_0_field;
} OIF_I2S_SPDIF_REG_1_UNION;

// OIF_I2S_SPDIF_REG_2
// OIF_CLOCK_DEF_PART_2 register type definition
// OIF_I2S_INPUT_CONTROL
/* I2S_INPUT_CONTROL (Auido Dac) register type definition */
typedef struct
{
  UInt  i2s_ratio         : 5; // Bit 0-4
  UInt  word_ratio        : 2; // Bit 5-6
  UInt  extern_clock_mux  : 1; // Bit 7
  UInt                    : 24;
} OIF_CLOCK_DEF_PART_2_STRUCT;

/* I2S_INPUT_CONTROL (Auido Dac) register type definition */
typedef struct
{
  UInt  i2s_clk_polarity  : 1; // Bit 0
  UInt  i2s_wclk_polarity : 1; // Bit 1
  UInt  i2s_data_polarity : 1; // Bit 2
  UInt  i2s_sp_format     : 1; // Bit 3
  UInt  parallel_mode     : 1; // Bit 4
  UInt  ad_mclk_polarity  : 1; // Bit 5
  UInt  ad_mute           : 1; // Bit 6
  UInt  ad_deemphasis     : 1; // Bit 7
  UInt                    : 24;
} OIF_I2S_INPUT_CONTROL_STRUCT;

typedef union
{
  uint32 all;
  OIF_CLOCK_DEF_PART_2_STRUCT mux_0_field;
  OIF_I2S_INPUT_CONTROL_STRUCT mux_1_field;
} OIF_I2S_SPDIF_REG_2_UNION;

//OIF_SP_CFG
typedef struct
{
 UInt int_spdif_mute           : 1;  // Bit 0
 UInt int_i2s_mute             : 1;  // Bit 1
 UInt int_frame_complete       : 1;  // Bit 2
 UInt en_int_mute              : 1;  // Bit 3
 UInt en_int_frame_complete    : 1;  // Bit 4
 UInt Sel_Fsout                : 1;  // Bit 5
 UInt sys_clock_switch         : 2;  // Bit 6-7
 UInt                          : 24;
} OIF_SP_CFG_STRUCT;

typedef union
{
 OIF_SP_CFG_STRUCT field;
 uint32 all;
} OIF_SP_CFG_UNION;


//OIF_SP_CTRL
typedef struct
{
 UInt mute_boundary_mode       : 1;  // Bit 0
 UInt en_compress              : 1;  // Bit 1
 UInt en_shockproof            : 1;  // Bit 2
 UInt monitor_buffer           : 1;  // Bit 3
 UInt                          : 4;  // Bit 4-7
 UInt                          : 24;
} OIF_SP_CTRL_STRUCT;

typedef union
{
 OIF_SP_CTRL_STRUCT field;
 uint32 all;
} OIF_SP_CTRL_UNION;


/* CD TEXT */


/* CD_TEXT_CONTROL register type definition */
typedef struct
{
  UInt  bit0                  : 1; // Bit 0
  UInt  cd_txt_rst_n          : 1; // Bit 1
  UInt  q_crc_check_rst_n     : 1; // Bit 2
  UInt  en_cd_txt_rcv         : 1; // Bit 3
  UInt  en_only_good_crc      : 1; // Bit 4
  UInt  cd_txt_overflow       : 1; // Bit 5
  UInt  cd_txt_rcv            : 1; // Bit 6
  UInt  cd_txt_crc_check      : 1; // Bit 7
  UInt                        : 24;
} OIF_CD_TEXT_CONTROL_STRUCT;

typedef union
{
  uint32 all;
  OIF_CD_TEXT_CONTROL_STRUCT field;
} OIF_CD_TEXT_CONTROL_UNION;