acqdef.h

本程序为ST公司开发的源代码

/**************************************************
 *
 *
 * CVS ID:   $Id: acqdef.h,v 1.4 2007/08/14 15:27:43 dellorto Exp $
 * Author:   Maurizio Marcucci [MM] - STM
 * Date:     $Date: 2007/08/14 15:27:43 $
 * Revision: $Revision: 1.4 $
 * 
 * Description:
 * 
 *   Accordo+ Hardware registers definition
 *
 ***************************************************
 * 
 * COPYRIGHT (C) ST Microelectronics  2005
 *            All Rights Reserved
 *
 ***************************************************/

/* ACQ_STATUS register type definition */
typedef struct
{
  UInt  unlocked          : 1;
  UInt  crc_ok            : 1;
  UInt  r_sec             : 1;
  UInt  a_sec             : 1;
  UInt  nsi_int           : 1;
  UInt  lba_int           : 1;
  UInt  lba_reached_int   : 1;
  UInt  dfct_int          : 1;
  UInt                    : 24;
} ACQ_STATUS_STRUCT;

typedef union
{
  uint32 all;
  ACQ_STATUS_STRUCT field;
} ACQ_STATUS_UNION;


/* ACQ_INT_CTRL register type definition */
typedef struct
{
  UInt  acq_pwr_on          : 1;
  UInt  acq_reset           : 1;
  UInt  mask_bad_crcs       : 1;
  UInt  sec_int_en          : 1;
  UInt  nsl_int_en          : 1;
  UInt  lba_int_en          : 1;
  UInt  lba_reached_int_en  : 1;
  UInt  dfct_int_en         : 1;
  UInt                      : 24;
} ACQ_INT_CTRL_STRUCT;

typedef union
{
  uint32 all;
  ACQ_INT_CTRL_STRUCT field;
} ACQ_INT_CTRL_UNION;

/* ACQ_PLL_CTRL1 register type definition */
typedef struct
{
  UInt  relock            : 1;
  UInt  auto_relock       : 1;
  UInt  force_media       : 1;
  UInt  cd_mode           : 1;
  UInt  toc_mode          : 1;
  UInt  ill_rl_cor        : 1;
  UInt  unlock_int        : 1;
  UInt  unlock_int_en     : 1;
  UInt                    : 24;
} ACQ_PLL_CTRL1_STRUCT;

typedef union
{
  uint32 all;
  ACQ_PLL_CTRL1_STRUCT field;
} ACQ_PLL_CTRL1_UNION;

/* ACQ_PLL_CTRL2 register type definition */
typedef struct
{
  UInt  fine_slice_en     : 1;
  UInt  force_slice       : 1;
  UInt  frz_slice_dfct    : 1;
  UInt  frz_boost_dfct    : 1;
  UInt  frz_frq_dfct      : 1;
  UInt  sel_acq_defect    : 2;
  UInt  no_event_dfct     : 1;
  UInt                    : 24;
} ACQ_PLL_CTRL2_STRUCT;

typedef union
{
  uint32 all;
  ACQ_PLL_CTRL2_STRUCT field;
} ACQ_PLL_CTRL2_UNION;

/* ACQ_PLL_GAINS register type definition */
typedef struct
{
  UInt  phase             : 4;
  UInt  frequency         : 4;
  UInt                    : 24;
} ACQ_PLL_GAINS_STRUCT;

typedef union
{
  uint32 all;
  ACQ_PLL_GAINS_STRUCT field;
} ACQ_PLL_GAINS_UNION;

/* ACQ_SLICER_GAINS register type definition */
typedef struct
{
  UInt  base              : 4;
  UInt  slc_viol          : 4;
  UInt                    : 24;
} ACQ_SLICER_GAINS_STRUCT;

typedef union
{
  uint32 all;
  ACQ_SLICER_GAINS_STRUCT field;
} ACQ_SLICER_GAINS_UNION;

/* ACQ_SLICER_CTRL register type definition */
typedef struct
{
  UInt  offset            : 4;
  UInt  gain_fineslc      : 4;
  UInt                    : 24;
} ACQ_SLICER_CTRL_STRUCT;

typedef union
{
  uint32 all;
  ACQ_SLICER_CTRL_STRUCT field;
} ACQ_SLICER_CTRL_UNION;

/* ACQ_EFM_CTRL1 register type definition */
typedef struct
{
  UInt  efm_win           : 3;
  UInt  bit3              : 1;
  UInt  bit4              : 1;
  UInt  bit5              : 1;
  UInt  bit6              : 1;
  UInt  bit7              : 1;
  UInt                    : 24;
} ACQ_EFM_CTRL1_STRUCT;

typedef union
{
  uint32 all;
  ACQ_EFM_CTRL1_STRUCT field;
} ACQ_EFM_CTRL1_UNION;

/* ACQ_EFM_CTRL2 register type definition */
typedef struct
{
  UInt  bit0              : 1;
  UInt  s0_interp_bypass  : 1;
  UInt  bit2              : 1;
  UInt  bit3              : 1;
  UInt  stop_byteclk      : 1;
  UInt  auto_buffer       : 1;
  UInt  bit6              : 1;
  UInt  bit7              : 1;
  UInt                    : 24;
} ACQ_EFM_CTRL2_STRUCT;

typedef union
{
  uint32 all;
  ACQ_EFM_CTRL2_STRUCT field;
} ACQ_EFM_CTRL2_UNION;


/* ACQ_CHA_CTRL1 register type definition */
typedef struct
{
  UInt  dec_ratio         : 2;
  UInt  bit2              : 1;
  UInt  bit3              : 1;
  UInt  bit4              : 1;
  UInt  bit5              : 1;
  UInt  bit6              : 1;
  UInt  bit7              : 1;
  UInt                    : 24;
} ACQ_CHA_CTRL1_STRUCT;

typedef union
{
  uint32 all;
  ACQ_CHA_CTRL1_STRUCT field;
} ACQ_CHA_CTRL1_UNION;

/* ACQ_CHA_CTRL2 register type definition */
typedef struct
{
  UInt  eq_bypass         : 1;
  UInt  force_boost       : 1;
  UInt  hpf_fc            : 2;
  UInt  squelch_en        : 1;
  UInt  bit5              : 1;
  UInt  cor_boost_en      : 1;
  UInt  bit7              : 1;
  UInt                    : 24;
} ACQ_CHA_CTRL2_STRUCT;

typedef union
{
  uint32 all;
  ACQ_CHA_CTRL2_STRUCT field;
} ACQ_CHA_CTRL2_UNION;


/* ACQ_BOOST register type definition */
typedef struct
{
  UInt  boost_offset      : 6;
  UInt  loop_gain         : 2;
  UInt                    : 24;
} ACQ_BOOST_STRUCT;

typedef union
{
  uint32 all;
  ACQ_BOOST_STRUCT field;
} ACQ_BOOST_UNION;

/* ACQ_DEFECT_MUX register type definition */
typedef struct
{
  UInt  freeze    : 2;
  UInt  squelch   : 2;
  UInt  dsp       : 2;
  UInt  erasure   : 2;
  UInt            : 24;
} ACQ_DEFECT_MUX_STRUCT;

typedef union
{
  uint32 all;
  ACQ_DEFECT_MUX_STRUCT field;
} ACQ_DEFECT_MUX_UNION;


/* ACQ_DEFECT_CTRL1 register type definition */
typedef struct
{
  UInt  thres     : 4;
  UInt  width     : 2;
  UInt  filter    : 2;
  UInt            : 24;
} ACQ_DEFECT_CTRL1_STRUCT;

typedef union
{
  uint32 all;
  ACQ_DEFECT_CTRL1_STRUCT field;
} ACQ_DEFECT_CTRL1_UNION;