sdci.h

来自「本程序为ST公司开发的源代码」· C头文件 代码 · 共 239 行

/**************************************************
 *
 * sdci.h
 *
 * CVS ID:   $Id: sdci.h,v 1.7 2007/02/27 09:29:35 belardi Exp $
 * Author:   Sangwon Bae [swbae] - Optomech
 * Date:     $Date: 2007/02/27 09:29:35 $
 * Revision: $Revision: 1.7 $
 * 
 * Description:
 * 
 *
 ***************************************************
 * 
 * COPYRIGHT (C) Optomech  2006
 *            All Rights Reserved
 *
 ***************************************************
 *
 * STM CVS Log:
 *
 * $Log: sdci.h,v $
 * Revision 1.7  2007/02/27 09:29:35  belardi
 * Optomech patch 070226
 * - MMC is supported by SDC driver
 *
 * Revision 1.6  2007/02/08 12:39:48  belardi
 * Optomech driver stability patch P070131
 *
 * Revision 1.5  2006/12/13 09:24:52  belardi
 * Optomech stability fix for SDC driver (P061212)
 *
 * Revision 1.4  2006/09/18 09:55:24  belardi
 * Corrected CVS keyword usage
 *
 * Revision 1.3  2006/09/18 09:25:23  belardi
 * Added Log CVS keyword into file header
 *
 *
 ***************************************************/
#ifndef __OPTO_SDCI_H__
#define __OPTO_SDCI_H__

#define SDW_CLK_INIT            (80)        // > 72
#define SDW_CLK_NCS             (16)
#define SDW_CLK_CMD             (64)
#define SDW_CLK_NCR             (9)         // cheat for o/i switching
#define SDW_CLK_RES             (63)
#define SDW_CLK_REX_R2          (8)
#define SDW_CLK_REX_R3          (32)
#define SDW_CLK_NCX             (64)
#define SDW_CLK_REG             (120)       // (16 - 1) * 8
#define SDW_CLK_BLK             (4088)      // (512 - 1) * 8
#define SDW_CLK_NEC             (32)        // > 8 & expected crc

#define SDW_TRY_IDLE            (256)

#define SDP_OCR_33_IDX          (2)         // 23 - 20 bit
#define SDP_OCR_33_MSK          (0x30)      // 3.2 - 3.4

#define SDP_CSD_TAAC_IDX        (1)         // 119 - 112 bit
#define SDP_CSD_TAAC_UMSK       (0x07)      // time unit
#define SDP_CSD_TAAC_VOFFSET    (3)         // time value offset
#define SDP_CSD_TAAC_VMSK       (0x0F)      // time value
#define SDP_CSD_NSAC_IDX        (2)         // 111 - 104 bit
#define SDP_CSD_NSAC_UNIT       (100)       // from spec
#define SDP_CSD_RBL_IDX         (5)         // 87 - 80 bit
#define SDP_CSD_RBL_MSK         (0x0F)      // 83:80 READ_BL_LEN
#define SDP_CSD_RBL_512         (9)         // 2^9 = 512

#define SDP_ANSWERLEN           (5)
#define SDP_CSDLEN              (16)
#define SDP_BLOCKLEN            (512)
#define SDP_BUFFERLEN           (SDP_CSDLEN)  // no token & crc
#define SDP_ADDROFFSET          (SDP_CSD_RBL_512)   
#define SDP_NACMIN              (SDW_CLK_NCX)   // just > 8
#define SDP_NACDEFAULT          (25504)     // MAX NSAC & 8s multiple
#define SDP_SEC2ADDR            (SDP_CSD_RBL_512)
#define SDP_OFFSETMASK          (0x000001FF)

#define SDP_CLOCK_INIT          (170)
#define SDP_CLOCK_BURST         (8)

#define SDP_DATAERR_MSK         (0xF0)      // data error token

#define SDS_NONE                (0x00000000)
#define SDS_READY               (0x00000003)
#define SDS_ERROR               (0x00000081)

#ifndef NULL
#define NULL                    (0)
#endif

typedef enum _e_SDMode
{
    SDM_CS = 0,
    SDM_NCS,
    SDM_CMD,
    SDM_NCR,
    SDM_RES,
    SDM_REX,
    SDM_NCX,
    SDM_NAC,
    SDM_DAT,
    SDM_NEC
} e_SDMode;

typedef enum _e_SDCmd
{
    SDC_0                       = 0,
    SDC_GO_IDLE_STATE           = SDC_0,
    SDC_1                       = 1,
    SDC_SEND_OP_COND            = SDC_1,
    SDC_9                       = 9,
    SDC_SEND_CSD                = SDC_9,
    SDC_12                      = 12,
    SDC_STOP_TRANSMISSION       = SDC_12,
    SDC_16                      = 16,
    SDC_SET_BLOCKLEN            = SDC_16,
    SDC_17                      = 17,
    SDC_READ_SINGLE_BLOCK       = SDC_17,
    SDC_18                      = 18,
    SDC_READ_MULTIPLE_BLOCK     = SDC_18,
    SDAC_41                     = 41,
    SDAC_SEND_OP_COND           = SDAC_41,
    SDC_55                      = 55,
    SDC_APP_CMD                 = SDC_55,
    SDC_58                      = 58,
    SDC_READ_OCR                = SDC_58
} e_SDCmd;

typedef enum _e_SDRes
{
    SDR_1 = 0x00,
    SDR_2 = 0x01,
    SDR_3 = 0x02,
    SDR_R = 0x03,
    SDR_D = 0x04,
    SDR_B = 0x10
} e_SDRes;

typedef uint8 e_SDErr;

typedef union
{
  uint32 value;
  struct
  {           
    uint32 Inserted         :1;     // Inserted
    uint32 Ready            :1;     // Ready
    uint32 FAT              :2;
    uint32 MP3              :1;
    uint32 Gap              :6;
    uint32 Step             :4;
    uint32 Error            :1;     // Error
    uint32 Count            :14;    // counter
    uint32 Pad              :2;
  } f;
} SDC_FLAG_STATUS;

#define SDE_OK                (0x00)
#define SDE_IN_IDLE_STATE     (0x01)
#define SDE_ILLEGAL_COMMAND   (0x04)
#define SDE_DATA_ERROR        (0x0F)
#define SDE_TIME_OUT          (0xFF)

#define SDC_STEP_SUPPLY       (0)
#define SDC_STEP_RESET        (1)
#define SDC_STEP_WAKEUP       (2)
#define SDC_STEP_READOCR      (3)
//#define SDC_STEP_SENDCSD      (4)
#define SDC_STEP_SETBL        (4) //(5)
#define SDC_STEP_DONE         (5) //(6)
#define SDC_STEP_FAIL         (6) //(7)

#define fat_load8(b,n)  ((b)[(n)])
#define fat_load16(b,n) ((b)[(n)]|((b)[(n)+1]<<8))
#define fat_load32(b,n) ((b)[(n)]|((b)[(n)+1]<<8)|((b)[(n)+2]<<16)|((b)[(n)+3]<<24))

#define SD_CSR1         BSPI1_CSR1
#define SD_CSR2         BSPI1_CSR2
#define SD_CSR3         BSPI1_CSR3
#define SD_CLK          BSPI1_CLK
#define SD_TXR          BSPI1_TXR
#define SD_RXR          BSPI1_RXR

#define SD_SIR          EIC_SIR_13

#define SD_ELAPSE_INSERTION       	T500ms
#define SD_ELAPSE_DETECTION       	T10ms
#define SD_ELAPSE_REMOVAL         	T100ms //T1000ms
#define SD_ELAPSE_MONITOR         	T100ms //T1000ms

#define SD_CLOCK_SUPPLY				(10)

#define SDC_DATA_FSM_IDLE			(0)
#define SDC_DATA_FSM_READ			(1)
#define SDC_DATA_FSM_DONE			(2)
#define SDC_DATA_FSM_ERROR			(3)

#define CTR_TRANSITION_SDC_TEST_FOR_SDC	(1)
#define CTR_TRANSITION_SDC_DATA_FOR_SDC	(2)

void	sd_init(void);

void	sdc_process_preevents(void);
void	sdc_transition_handler(void);

uint16	sdc_xfer_transition(void);

void	  sdc_set_error(t_fsm *sdc_fsm, GRESULT error_reason);

void    sdc_test_back(void);

RETVAL  sd_detect(void);
RETVAL  sd_check(void);

GRESULT sd_reset(void);
GRESULT sd_wakeup(void);
GRESULT sd_readocr(void);
GRESULT sd_sendcsd(void);
GRESULT sd_setbl(void);

e_SDErr sd_command(e_SDCmd cmd, tU32 param, e_SDRes res);
e_SDErr sd_open(tU32 addr, tU32 offset, tU8* dest, tU32 size);
e_SDErr sd_wait(void);
e_SDErr sd_query(e_SDCmd cmd, tU32 param);
e_SDErr sd_close(void);

void sd_reset_clock(void);
void sd_burst_clock(void);

void sd_delay(tU32 cnt);
void sd_send(tU8 dat);
tU8 sd_read(tU8 dat);
void sdc_glb_isr(void);

#endif /* __OPTO_SDCI_H__ */