st79.h

我个人编写的车载dvd上的程序

ext volatile UCharField U_FLASH_CR2 @0x505B;//Flash control register 2
ext volatile UCharField U_FLASH_NCR2 @0x505C;//Flash complementary control register
ext volatile UCharField U_FLASH_FPR @0x505D;//Flash protection register
ext volatile UCharField U_FLASH_NFPR @0x505E;//Flash complementary protection register
ext volatile UCharField U_FLASH_IAPSR @0x505F;//Flash in-application programming status register
ext volatile UCharField U_FLASH_PUKR @0x5062;//Flash program memory unprotection key register
ext volatile UCharField U_FLASH_DUKR @0x5064;//Data EEPROM unprotection register
#define FLASH_CR1                      U_FLASH_CR1.byte
#define FLASH_CR2                      U_FLASH_CR2.byte
#define FLASH_NCR2                     U_FLASH_NCR2.byte
#define FLASH_FPR                      U_FLASH_FPR.byte
#define FLASH_NFPR                     U_FLASH_NFPR.byte
#define FLASH_IAPSR                    U_FLASH_IAPSR.byte
#define FLASH_PUKR                     U_FLASH_PUKR.byte
#define FLASH_DUKR                     U_FLASH_DUKR.byte



//Opt
ext volatile UCharField U_OPT0 @0x5067;
ext volatile UCharField U_NOPT0 @0x5068;
ext volatile UCharField U_OPT1 @0x5069;
ext volatile UCharField U_NOPT1 @0x506A;
ext volatile UCharField U_OPT2 @0x506B;
ext volatile UCharField U_NOPT2 @0x506C;
ext volatile UCharField U_OPT3 @0x506D;
ext volatile UCharField U_NOPT3 @0x506E;
#define OPTO                           U_OPT0.byte
#define NOPTO                          U_NOPT0.byte
#define OPT1                           U_OPT1.byte
#define NOPT1                          U_NOPT1.byte
#define OPT2                           U_OPT2.byte
#define NOPT2                          U_NOPT2.byte
#define OPT3                           U_OPT3.byte
#define NOPT3                          U_NOPT3.byte

ext volatile UCharField U_EXTI_CR1 @0x50A0;//external interrupt control register 1
ext volatile UCharField U_EXTI_CR2 @0x50A1;//external interrupt control register 2
#define EXTI_CR1                    U_EXTI_CR1.byte
#define EXTI_CR2                    U_EXTI_CR2.byte

//RST
ext volatile UCharField U_RST_SR @0x50B0;//Reset status register
#define RST_SR                         U_RST_SR.byte

//CLK
ext volatile UCharField U_CLK_ICKR @0x50C0;//Internal clock register
ext volatile UCharField U_CLK_ECKR @0x50C1;//external clock register
ext volatile UCharField U_CLK_CMSR @0x50C3;//Clock master status register
ext volatile UCharField U_CLK_SWR @0x50C4;//Clock master switch register
ext volatile UCharField U_CLK_SWCR @0x50C5;//Switch control register
ext volatile UCharField U_CLK_CKDIVR @0x50C6;//Clock divider register
ext volatile UCharField U_CLK_PCKENR1 @0x50C7;//Peripheral clock gating register 1
ext volatile UCharField U_CLK_CSSR @0x50C8;//Clock security system register
ext volatile UCharField U_CLK_CCOR @0x50C9;//Configurable clock output register
ext volatile UCharField U_CLK_HSESTR @0x50CA;//HSE clock startup time register
ext volatile UCharField U_CLK_PCKENR2 @0x50CB;//Peripheral clock gating register 2
ext volatile UCharField U_CLK_HSICALR @0x50CC;//HSI clock calibration register
ext volatile UCharField U_CLK_NHSICALR @0x50CD;//Complementary HSI clock calibration register
ext volatile UCharField U_CLK_HSITRIMR @0x50CE;//HSI clock calibration trimming register
#define CLK_ICKR                     U_CLK_ICKR.byte
#define CLK_ICKR_HSIEN               U_CLK_ICKR.field.B0  //High speed internal RC oscillator enable
#define CLK_ICKR_HSIRDY              U_CLK_ICKR.field.B1  //High speed internal oscillator ready
#define CLK_ICKR_FHW                 U_CLK_ICKR.field.B2  //Fast Wake-up from Active Halt/Halt mode
#define CLK_ICKR_LSIEN               U_CLK_ICKR.field.B3  //Low speed internal RC oscillator enable
#define CLK_ICKR_LSIRDY               U_CLK_ICKR.field.B4  //Low speed internal oscillator ready
#define CLK_ICKR_SHW                 U_CLK_ICKR.field.B5   //Slow Wake-up from Active Halt/Halt modes



#define CLK_ECKR                     U_CLK_ECKR.byte
#define CLK_ECKR_HSEEN               U_CLK_ECKR.field.B0  //High speed external crystal oscillator enable
#define CLK_ECKR_HSERDY              U_CLK_ECKR.field.B1  //High speed external crystal oscillator ready

#define CLK_CMSR                     U_CLK_CMSR.byte
#define CLK_SWR                      U_CLK_SWR.byte
#define CLK_SWCR                     U_CLK_SWCR.byte
#define CLK_SWCR_SWBSY               U_CLK_SWCR.field.B0  //Switch busy
#define CLK_SWCR_SWEN                U_CLK_SWCR.field.B1  //Switch start/stop
#define CLK_SWCR_SWIEN               U_CLK_SWCR.field.B2  //Clock switch interrupt enable
#define CLK_SWCR_SWIF                U_CLK_SWCR.field.B3  //Clock switch interrupt flag

#define CLK_CKDIVR                   U_CLK_CKDIVR.byte
#define CLK_PCKENR1                  U_CLK_PCKENR1.byte
#define CLK_CSSR                     U_CLK_CSSR.byte
#define CLK_CCOR                     U_CLK_CCOR.byte
#define CLK_HSESTR                   U_CLK_HSESTR.byte
#define CLK_PCKENR2                  U_CLK_PCKENR2.byte
#define CLK_HSICALR                  U_CLK_HSICALR.byte
#define CLK_NHSICALR                 U_CLK_NHSICALR.byte
#define CLK_HSITRIMR                 U_CLK_HSITRIMR.byte

//Window watchdog---WWDG
ext volatile UCharField U_WWDG_CR @0x50D1;//Control Register
ext volatile UCharField U_WWDG_WR @0x50D2;//Window Register
#define WWDG_CR                    U_WWDR_CR.byte
#define WWDG_WR                    U_WWDR_WR.byte

//Independent Watchdog (IWDG)
ext volatile UCharField U_IWDG_KR @0x50E0;//Key register
ext volatile UCharField U_IWDG_PR @0x50E1;//Prescaler register
ext volatile UCharField U_IWDG_RLR @0x50E2;//Reload register
#define IWDG_KR                    U_IWDR_KR.byte
#define IWDG_PR                    U_IWDR_PR.byte
#define IWDG_RLR                   U_IWDR_RLR.byte

//Auto Wake-up
ext volatile UCharField U_AWU_CSR1 @0x50F0;//Control/Status register
ext volatile UCharField U_AWU_APR @0x50F1;//Asynchronous prescaler register
ext volatile UCharField U_AWU_TBR @0x50F2;//Timebase selection register
ext volatile UCharField U_AWU_CSR2 @0x50F3;//Control/Status register 2
#define AWU_CSR1                   U_AWU_CSR1.byte
#define AWU_APR                    U_AWU_APR.byte
#define AWU_TBR                    U_AWU_TBR.byte
#define AWU_CSR2                   U_AWU_CSR2.byte
//Spi
ext volatile UCharField U_SPI_CR1 @0x5200;//SPI control register 1
ext volatile UCharField U_SPI_CR2 @0x5201;//SPI control register 2
ext volatile UCharField U_SPI_ICR @0x5202;//SPI Interrupt Control Register
ext volatile UCharField U_SPI_SR @0x5203;//SPI Status Register
ext volatile UCharField U_SPI_DR @0x5204;//SPI Data Register
ext volatile UCharField U_SPI_CRCPR @0x5205;//SPI CRC Polynomial Register
ext volatile UCharField U_SPI_RXCRCR @0x5206;//SPI Rx CRC Register
ext volatile UCharField U_SPI_TXCRCR @0x5207;//SPI Tx CRC Register
#define SPI_CR1                   U_SPI_CR1.byte
#define SPI_CR1_CPHA         U_SPI_CR1.field.B0 //Clock Phase
#define SPI_CR1_CPOL         U_SPI_CR1.field.B1 //Clock Polarity
#define SPI_CR1_MSTR         U_SPI_CR1.field.B2 //Master Selection
#define SPI_CR1_SPE           U_SPI_CR1.field.B6 //SPI Enable
#define SPI_CR1_LSBFIRST  U_SPI_CR1.field.B7 //Frame Format

#define SPI_CR2                   U_SPI_CR2.byte
#define SPI_CR2_SSI               U_SPI_CR2.field.B0  //Internal slave select;0: Slave,1: Master
#define SPI_CR2_SSM               U_SPI_CR2.field.B1  //Software slave management;0: disable,1: enable
#define SPI_CR2_RXONLY            U_SPI_CR2.field.B2  //Receive only;0: Full-duplex (Transmit and receive),1: Output disabled (Receive only mode)
#define SPI_CR2_CRCNEXT           U_SPI_CR2.field.B4  //Transmit CRC next;0: Next transmit value is from Tx buffer 1: Next transmit value is from Tx CRC register
#define SPI_CR2_CRCEN             U_SPI_CR2.field.B5  //Hardware CRC calculation enable,0: disable,1: enable
#define SPI_CR2_BDOE              U_SPI_CR2.field.B6  //Output enable in bi-directional mode;0:Output disabled,1:Output enabled
#define SPI_CR2_BDM               U_SPI_CR2.field.B7  //Bi-directional data mode enable;0:2-line uni-directional data mode,1:1-line bi-directional data mode

#define SPI_ICR                   U_SPI_ICR.byte
#define SPI_ICR_WKIE              U_SPI_ICR.field.B4 //Wake-up interrupt enable
#define SPI_ICR_ERRE              U_SPI_ICR.field.B5 //Error interrupt enable
#define SPI_ICR_RXIE              U_SPI_ICR.field.B6 //RX buffer not empty interrupt enable
#define SPI_ICR_TXIE              U_SPI_ICR.field.B7 //Tx buffer empty interrupt enable

#define SPI_SR                    U_SPI_SR.byte
#define SPI_SR_RxNE               U_SPI_SR.field.B0 //Receive buffer not empty,0: Rx buffer empty,1: Rx buffer not empty
#define SPI_SR_TXE                U_SPI_SR.field.B1 //Transmit buffer empty;0: Tx buffer not empty,1: Tx buffer empty
#define SPI_SR_WKUP               U_SPI_SR.field.B3 //Wake-up Flag;0 : No Wake-up occured,1: Wake-up event occurred
#define SPI_SR_CRCERR             U_SPI_SR.field.B4 //CRC error flag
#define SPI_SR_MODF               U_SPI_SR.field.B5 //Mode fault
#define SPI_SR_OVR                U_SPI_SR.field.B6 //Overrun flag
#define SPI_SR_BSY                U_SPI_SR.field.B7 //Busy flag

#define SPI_DR                    U_SPI_DR.byte
#define SPI_CRCPR                 U_SPI_CRCPR.byte
#define SPI_RXCRCR                U_SPI_RXCRCR.byte
#define SPI_TXCRCR                U_SPI_TXCRCR.byte

//I2C
ext volatile UCharField U_I2C_CR1 @0x5210;//Control register 1
ext volatile UCharField U_I2C_CR2 @0x5211;//Control register 2
ext volatile UCharField U_I2C_FREQR @0x5212;//Frequency register
ext volatile UCharField U_I2C_OARL @0x5213;//Own address register LSB
ext volatile UCharField U_I2C_OARH @0x5214;//Own address register MSB
ext volatile UCharField U_I2C_DR @0x5216;//Data register
ext volatile UCharField U_I2C_SR1 @0x5217;//Status register 1
ext volatile UCharField U_I2C_SR2 @0x5218;//Status register 2
ext volatile UCharField U_I2C_SR3 @0x5219;//Status register 3
ext volatile UCharField U_I2C_ITR @0x521A;//Interrupt register
ext volatile UCharField U_I2C_CCRL @0x521B;//Clock control register low
ext volatile UCharField U_I2C_CCRH @0x521C;//Clock control register High
ext volatile UCharField U_I2C_TRISER @0x521D;//TRISE Register
ext volatile UCharField U_I2C_PECR @0x521E;//Packet Error Checking Register
#define I2C_CR1                   U_I2C_CR1.byte
#define I2C_CR1_PE                U_I2C_CR1.field.B0
#define I2C_CR1_ENGC              U_I2C_CR1.field.B6
#define I2C_CR1_NOSTRETCH         U_I2C_CR1.field.B7

#define I2C_CR2                   U_I2C_CR2.byte
#define I2C_CR2_START             U_I2C_CR2.field.B0
#define I2C_CR2_STOP              U_I2C_CR2.field.B1
#define I2C_CR2_ACK               U_I2C_CR2.field.B2
#define I2C_CR2_POS               U_I2C_CR2.field.B3
#define I2C_CR2_SWRST             U_I2C_CR2.field.B7


#define I2C_FREQR                 U_I2C_FREQR.byte
#define I2C_OARL                  U_I2C_OARL.byte
#define I2C_OARH                  U_I2C_OARH.byte
#define I2C_OARH_ADDMODE          U_I2C_OARH.field.B7

#define I2C_DR                    U_I2C_DR.byte

#define I2C_SR1                   U_I2C_SR1.byte     //READ ONLY
#define I2C_SR1_SB                U_I2C_SR1.field.B0   //Start Bit (Master mode)
#define I2C_SR1_ADDR              U_I2C_SR1.field.B1  //Address sent (master mode)/matched (slave mode)
#define I2C_SR1_BTF               U_I2C_SR1.field.B2  //Byte Transfer Finished
#define I2C_SR1_ADD10             U_I2C_SR1.field.B3  //10-bit header sent (Master mode)
#define I2C_SR1_STOPF             U_I2C_SR1.field.B4  //Stop detection (Slave mode)
#define I2C_SR1_RxNE              U_I2C_SR1.field.B6  //Data Register not Empty (receivers)
#define I2C_SR1_TxE               U_I2C_SR1.field.B7  //Data Register Empty (transmitters)


#define I2C_SR2                   U_I2C_SR2.byte      //READ ONLY
#define I2C_SR2_BERR              U_I2C_SR2.field.B0 //Bus Error
#define I2C_SR2_ARLO              U_I2C_SR2.field.B1  //Arbitration Lost (master mode)
#define I2C_SR2_AF                U_I2C_SR2.field.B2  //Acknowledge Failure.
#define I2C_SR2_OVR               U_I2C_SR2.field.B3  //Overrun/Underrun
#define I2C_SR2_WUFH              U_I2C_SR2.field.B5   //Wake-up from Halt

#define I2C_SR3                   U_I2C_SR3.byte //READ ONLY
#define I2C_SR3_MSL               U_I2C_SR3.field.B0 //Master/Slave
#define I2C_SR3_BUSY              U_I2C_SR3.field.B1 //Bus Busy
#define I2C_SR3_TRA               U_I2C_SR3.field.B2 //Transmitter/Receiver
#define I2C_SR3_GENCALL           U_I2C_SR3.field.B4 //General Call Header (Slave mode)

#define I2C_ITR                   U_I2C_ITR.byte
#define I2C_ITR_ITERREN           U_I2C_ITR.field.B0  //Error Interrupt Enable
#define I2C_ITR_ITEVTEN           U_I2C_ITR.field.B1 //Event Interrupt Enable
#define I2C_ITR_ITBUFEN           U_I2C_ITR.field.B2 //Buffer Interrupt Enable

#define I2C_CCRL                  U_I2C_CCRL.byte
#define I2C_CCRH                  U_I2C_CCRH.byte
#define I2C_TRISER                U_I2C_TRISER.byte
#define I2C_PECR                  U_I2C_PECR.byte


//Usart
ext volatile UCharField U_USART_SR @0x5230;//Status Register
ext volatile UCharField U_USART_DR @0x5231;//Data Register
ext volatile UCharField U_USART_BRR1 @0x5232;//Baud Rate Register 1
ext volatile UCharField U_USART_BRR2 @0x5233;//Baud Rate Register 2
ext volatile UCharField U_USART_CR1 @0x5234;//Control Register 1
ext volatile UCharField U_USART_CR2 @0x5235;//Control Register 2
ext volatile UCharField U_USART_CR3 @0x5236;//Control Register 3
ext volatile UCharField U_USART_CR4 @0x5237;//Control Register 4
ext volatile UCharField U_USART_CR5 @0x5238;//Control Register 5 
ext volatile UCharField U_USART_GTR @0x5239;//Guard time register
ext volatile UCharField U_USART_PSCR @0x523A;//Prescaler register
#define USART_SR                   U_USART_SR.byte
#define USART_DR                   U_USART_DR.byte
#define USART_BRR1                 U_USART_BRR1.byte
#define USART_BRR2                 U_USART_BRR2.byte
#define USART_CR1                  U_USART_CR1.byte
#define USART_CR2                  U_USART_CR2.byte
#define USART_CR3                  U_USART_CR3.byte
#define USART_CR4                  U_USART_CR4.byte
#define USART_CR5                  U_USART_CR5.byte
#define USART_GTR                  U_USART_GTR.byte
#define USART_PSCR                 U_USART_PSCR.byte

//Linuart
ext volatile UCharField U_LINUART_SR @0x5240;//Status Register
ext volatile UCharField U_LINUART_DR @0x5241;//Data Register