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/* -------- ADDRESS REGISTERS ------------------------ */
#define AT91RM9200_REG_EMAC_HSH_OFFSET 0x90 /* EMAC Hash Address High [63:32] */
#define AT91RM9200_REG_EMAC_HSL_OFFSET 0x94 /* EMAC Hash Address Low [31:0] */
#define AT91RM9200_REG_EMAC_SA1L_OFFSET 0x98 /* EMAC Specific Address 1 Low, First 4 bytes */
#define AT91RM9200_REG_EMAC_SA1H_OFFSET 0x9C /* EMAC Specific Address 1 High, Last 2 bytes */
#define AT91RM9200_REG_EMAC_SA2L_OFFSET 0xA0 /* EMAC Specific Address 2 Low, First 4 bytes */
#define AT91RM9200_REG_EMAC_SA2H_OFFSET 0xA4 /* EMAC Specific Address 2 High, Last 2 bytes */
#define AT91RM9200_REG_EMAC_SA3L_OFFSET 0xA8 /* EMAC Specific Address 3 Low, First 4 bytes */
#define AT91RM9200_REG_EMAC_SA3H_OFFSET 0xAC /* EMAC Specific Address 3 High, Last 2 bytes */
#define AT91RM9200_REG_EMAC_SA4L_OFFSET 0xB0 /* EMAC Specific Address 4 Low, First 4 bytes */
#define AT91RM9200_REG_EMAC_SA4H_OFFSET 0xB4 /* EMAC Specific Address 4 High, Last 2 bytes */
/*
*********************************************************************************************************
* AT91RM9200 REGISTER BITS
*********************************************************************************************************
*/
/* -------- EMAC CONTROL REGISTER (CTL) BITS ----------------- */
#define AT91RM9200_REG_EMAC_CTL_LB_LOW DEF_BIT_NONE /* 0: Optional. Loopback signal LOW. Default. */
#define AT91RM9200_REG_EMAC_CTL_LB_HIGH DEF_BIT_00 /* 1: Optional. Loopback signal HIGH. */
#define AT91RM9200_REG_EMAC_CTL_LBL_DIS DEF_BIT_NONE /* 0: Loopback Local DISABLE. Default. */
#define AT91RM9200_REG_EMAC_CTL_LBL_EN DEF_BIT_01 /* 1: Loopback Local ENABLE. */
#define AT91RM9200_REG_EMAC_CTL_RE_DIS DEF_BIT_NONE /* 0: Receive DISABLE. Default. */
#define AT91RM9200_REG_EMAC_CTL_RE_EN DEF_BIT_02 /* 1: Receive ENABLE. */
#define AT91RM9200_REG_EMAC_CTL_TE_DIS DEF_BIT_NONE /* 0: Transmit DISABLE. Default. */
#define AT91RM9200_REG_EMAC_CTL_TE_EN DEF_BIT_03 /* 1: Transmit ENABLE. */
#define AT91RM9200_REG_EMAC_CTL_MPE_DIS DEF_BIT_NONE /* 0: Management Port DISABLE. Default. */
#define AT91RM9200_REG_EMAC_CTL_MPE_EN DEF_BIT_04 /* 1: Management Port ENABLE. */
#define AT91RM9200_REG_EMAC_CTL_CSR DEF_BIT_05 /* Write to clear Statistics Registers. */
#define AT91RM9200_REG_EMAC_CTL_ISR DEF_BIT_06 /* Write to Increment Statistics Registers FOR TEST USE. */
#define AT91RM9200_REG_EMAC_CTL_WES_DIS DEF_BIT_NONE /* 0: Normal operation of Statistics Registers. Default. */
#define AT91RM9200_REG_EMAC_CTL_WES_EN DEF_BIT_07 /* 1: Enable Write to Statistics Registers FOR TEST USE. */
#define AT91RM9200_REG_EMAC_CTL_BP_DIS DEF_BIT_NONE /* 0: Normal operation. Default. */
#define AT91RM9200_REG_EMAC_CTL_BP_EN DEF_BIT_08 /* 1: Force collision on all RX frames in HDX mode. */
/* -------- EMAC CONFIGURATION REGISTER (CFG) BITS ----------- */
#define AT91RM9200_REG_EMAC_CFG_SPD_10 DEF_BIT_NONE /* 0: Set 10 MBps Speed (no functional effect). Default. */
#define AT91RM9200_REG_EMAC_CFG_SPD_100 DEF_BIT_00 /* 1: Set 100 MBps Speed (no functional effect). */
#define AT91RM9200_REG_EMAC_CFG_HD DEF_BIT_NONE /* 0: Half Duplex Operation. Default. */
#define AT91RM9200_REG_EMAC_CFG_FD DEF_BIT_01 /* 1: Full Duplex Operation. */
#define AT91RM9200_REG_EMAC_CFG_BR DEF_BIT_NONE /* Bit Rate (optional: write 0). */
#define AT91RM9200_REG_EMAC_CFG_CAF_DIS DEF_BIT_NONE /* 0: Normal operation. Default. */
#define AT91RM9200_REG_EMAC_CFG_CAF_EN DEF_BIT_04 /* 1: All valid frames are received. */
#define AT91RM9200_REG_EMAC_CFG_NBC_DIS DEF_BIT_NONE /* 0: Normal operation. Default. */
#define AT91RM9200_REG_EMAC_CFG_NBC_EN DEF_BIT_05 /* 1: No broadcast frames are received. */
#define AT91RM9200_REG_EMAC_CFG_MTI_DIS DEF_BIT_NONE /* 0: Multicast Hash DISABLE. Default. */
#define AT91RM9200_REG_EMAC_CFG_MTI_EN DEF_BIT_06 /* 1: Multicast Hash ENABLE. */
#define AT91RM9200_REG_EMAC_CFG_UNI_DIS DEF_BIT_NONE /* 0: Unicast Hash DISABLE. Default. */
#define AT91RM9200_REG_EMAC_CFG_UNI_EN DEF_BIT_07 /* 1: Unicast Hash ENABLE. */
#define AT91RM9200_REG_EMAC_CFG_NORMAL DEF_BIT_NONE /* 0: Reception of 802.3 1518 byte (NORMAL) frames. Default. */
#define AT91RM9200_REG_EMAC_CFG_BIG DEF_BIT_08 /* 1: Reception of 802.3ac 1522 byte (VLAN) frames. */
#define AT91RM9200_REG_EMAC_CFG_EAE DEF_BIT_NONE /* External Address Match Enable (optional: write 0). */
#define AT91RM9200_REG_EMAC_CFG_CLK_8 DEF_BIT_NONE /* 00: MDC Clock = MCK divided by 8. */
#define AT91RM9200_REG_EMAC_CFG_CLK_16 (0x01 << 10) /* 01: MDC Clock = MCK divided by 16. */
#define AT91RM9200_REG_EMAC_CFG_CLK_32 (0x02 << 10) /* 10: MDC Clock = MCK divided by 32. Default. */
#define AT91RM9200_REG_EMAC_CFG_CLK_64 (0x03 << 10) /* 11: MDC Clock = MCK divided by 64. */
#define AT91RM9200_REG_EMAC_CFG_RTY_DIS DEF_BIT_NONE /* 0: Retry Test DISABLE. Default. */
#define AT91RM9200_REG_EMAC_CFG_RTY_EN DEF_BIT_12 /* 1: Retry Test ENABLE. (FOR TESTS ONLY). */
#define AT91RM9200_REG_EMAC_CFG_RMII_DIS DEF_BIT_NONE /* 0: MII Mode. Default. */
#define AT91RM9200_REG_EMAC_CFG_RMII_EN DEF_BIT_13 /* 1: Reduced MII Mode. */
/* -------- EMAC STATUS REGISTER (SR) BITS ------------------- */
#define AT91RM9200_REG_EMAC_SR_LINK DEF_BIT_00 /* Reserved. */
#define AT91RM9200_REG_EMAC_SR_MDIO_UNSET DEF_BIT_NONE /* 0: MDIO pin NOT set. */
#define AT91RM9200_REG_EMAC_SR_MDIO_SET DEF_BIT_01 /* 1: MDIO pin set. Default. */
#define AT91RM9200_REG_EMAC_SR_IDLE DEF_BIT_NONE /* 0: PHY logic is idle. */
#define AT91RM9200_REG_EMAC_SR_RUNNING DEF_BIT_02 /* 1: PHY logic running. Default. */
/* -------- EMAC TRANSMIT CONTROL REGISTER (TCR) BITS -------- */
#define AT91RM9200_REG_EMAC_TCR_LEN(_x_) (_x_ & 0x07FF) /* Transmit Frame Length minus CRC length (if any). */
#define AT91RM9200_REG_EMAC_TCR_CRC DEF_BIT_NONE /* 0: Append CRC on Transmit. Default. */
#define AT91RM9200_REG_EMAC_TCR_NCRC DEF_BIT_15 /* 1: Do NOT append CRC on Transmit. */
/* -------- EMAC TRANSMIT STATUS REGISTER (TSR) BITS --------- */
/* 0: No event. */
#define AT91RM9200_REG_EMAC_TSR_OVR DEF_BIT_00 /* 1: Ethernet Transmit Buffer Overrun. */
#define AT91RM9200_REG_EMAC_TSR_OVR_CLR DEF_BIT_00 /* 1: Clear event. */
#define AT91RM9200_REG_EMAC_TSR_COL DEF_BIT_01 /* 1: Collision Occurred. */
#define AT91RM9200_REG_EMAC_TSR_COL_CLR DEF_BIT_01 /* 1: Clear event. */
#define AT91RM9200_REG_EMAC_TSR_RLE DEF_BIT_02 /* 1: Retry Limit Exceeded. */
#define AT91RM9200_REG_EMAC_TSR_RLE_CLR DEF_BIT_02 /* 1: Clear event. */
#define AT91RM9200_REG_EMAC_TSR_TXIDLE DEF_BIT_03 /* 1: Transmitter Idle. */
#define AT91RM9200_REG_EMAC_TSR_TXIDLE_CLR DEF_BIT_03 /* 1: Clear event. */
#define AT91RM9200_REG_EMAC_TSR_BNQ DEF_BIT_04 /* 1: Ethernet Transmit Buffer not Queued. */
#define AT91RM9200_REG_EMAC_TSR_BNQ_CLR DEF_BIT_04 /* 1: Clear event. */
#define AT91RM9200_REG_EMAC_TSR_COMP DEF_BIT_05 /* 1: Transmit Complete. */
#define AT91RM9200_REG_EMAC_TSR_COMP_CLR DEF_BIT_05 /* 1: Clear event. */
#define AT91RM9200_REG_EMAC_TSR_UND DEF_BIT_06 /* 1: Transmit Underrun. */
#define AT91RM9200_REG_EMAC_TSR_UND_CLR DEF_BIT_06 /* 1: Clear event. */
/* -------- EMAC RECEIVE STATUS REGISTER (RSR) BITS ---------- */
/* 0: No event. */
#define AT91RM9200_REG_EMAC_RSR_BNA DEF_BIT_00 /* 1: Buffer Not Available. */
#define AT91RM9200_REG_EMAC_RSR_BNA_CLR DEF_BIT_00 /* 1: Clear event. */
#define AT91RM9200_REG_EMAC_RSR_REC DEF_BIT_01 /* 1: Frame Received. */
#define AT91RM9200_REG_EMAC_RSR_REC_CLR DEF_BIT_01 /* 1: Clear event. */
#define AT91RM9200_REG_EMAC_RSR_OVR DEF_BIT_02 /* 1: RX Overrun. */
#define AT91RM9200_REG_EMAC_RSR_OVR_CLR DEF_BIT_02 /* 1: Clear event. */
/* -------- EMAC INTERRUPT STATUS REGISTER (ISR) BITS ------- */
/* NOTE: Registers are cleared on read. */
/* -------- EMAC INTERRUPT ENABLE REGISTER (IER) BITS ------- */
/* -------- EMAC INTERRUPT DISABLE REGISTER (IDR) BITS ------- */
/* -------- EMAC INTERRUPT MASK REGISTER (IMR) BITS ------- */
/* 0: The corresponding interrupt is enabled. */
/* 1: The corresponding interrupt is disabled. */
/* NOTE: The interrupt is disabled when the corresponding bit */
/* is set. This is non-standard for AT91 products as generally */
/* a mask bit set enables the interrupt. */
#define AT91RM9200_REG_EMAC_INT_DONE DEF_BIT_00 /* PHY Management Complete. */
#define AT91RM9200_REG_EMAC_INT_RCOM DEF_BIT_01 /* Receive Complete. */
#define AT91RM9200_REG_EMAC_INT_RBNA DEF_BIT_02 /* Receive Buffer Not Available. */
#define AT91RM9200_REG_EMAC_INT_TOVR DEF_BIT_03 /* Transmit Buffer Overrun. */
#define AT91RM9200_REG_EMAC_INT_TUND DEF_BIT_04 /* Transmit Buffer Underrun. */
#define AT91RM9200_REG_EMAC_INT_RTRY DEF_BIT_05 /* Retry Limit. */
#define AT91RM9200_REG_EMAC_INT_TBRE DEF_BIT_06 /* Transmit Buffer Register Empty. */
#define AT91RM9200_REG_EMAC_INT_TCOM DEF_BIT_07 /* Transmit Complete. */
#define AT91RM9200_REG_EMAC_INT_TIDLE DEF_BIT_08 /* Transmit Idle. */
#define AT91RM9200_REG_EMAC_INT_LINK DEF_BIT_09 /* Link Pin Changed Value (optional). */
#define AT91RM9200_REG_EMAC_INT_ROVR DEF_BIT_10 /* RX Overrun. */
#define AT91RM9200_REG_EMAC_INT_ABT DEF_BIT_11 /* Abort on DMA transfer. */
/* -------- EMAC PHY MAINTENANCE REGISTER (MAN) BITS --------- */
#define AT91RM9200_REG_EMAC_MAN_DATA(_x_) (_x_ & 0xFFFF) /* PHY Read/Write Data Register. */
#define AT91RM9200_REG_EMAC_MAN_CODE (0x02 << 16) /* IEEE Code. MUST have value of 10. */
#define AT91RM9200_REG_EMAC_MAN_REGA(_x_) ((_x_ & 0x1F) << 18) /* Specifies the register in the PHY to access. */
#define AT91RM9200_REG_EMAC_MAN_PHYA(_x_) ((_x_ & 0x1F) << 23) /* PHY address. Normally 0. */
#define AT91RM9200_REG_EMAC_MAN_WRITE (0x01 << 28) /* 01: Transfer is a write. */
#define AT91RM9200_REG_EMAC_MAN_READ (0x02 << 28) /* 10: Transfer is a read. */
#define AT91RM9200_REG_EMAC_MAN_HIGH DEF_BIT_30 /* MUST be set to 1. */
#define AT91RM9200_REG_EMAC_MAN_LOW DEF_BIT_NONE /* MUST be set to 0. */
/*
*********************************************************************************************************
* AT91RM9200 RECEIVE BUFFER DESCRIPTOR
*********************************************************************************************************
*/
/* -------- WORD 0 - ADDRESS --------------------------------- */
#define AT91RM9200_EMAC_RXBUF_ADD_MAC_OWNED DEF_BIT_NONE /* 0: EMAC owns buffer. */
#define AT91RM9200_EMAC_RXBUF_ADD_SW_OWNED DEF_BIT_00 /* 1: Software owns the buffer. */
#define AT91RM9200_EMAC_RXBUF_ADD_NO_WRAP DEF_BIT_NONE /* 0: This is NOT the last buffer in the ring. */
#define AT91RM9200_EMAC_RXBUF_ADD_WRAP DEF_BIT_01 /* 1: This is the last buffer in the ring. */
#define AT91RM9200_EMAC_RXBUF_ADD_BASE_MASK 0xFFFFFFFC /* Base address of the receive buffer */
/* -------- WORD 1 - STATUS ---------------------------------- */
#define AT91RM9200_EMAC_RXBUF_STAT_LEN_MASK 0x07FF /* Length of frame including FCS. */
#define AT91RM9200_EMAC_RXBUF_STAT_LOC4 DEF_BIT_23 /* Local address match (Specific address 4 match). */
#define AT91RM9200_EMAC_RXBUF_STAT_LOC3 DEF_BIT_24 /* Local address match (Specific address 3 match). */
#define AT91RM9200_EMAC_RXBUF_STAT_LOC2 DEF_BIT_25 /* Local address match (Specific address 2 match). */
#define AT91RM9200_EMAC_RXBUF_STAT_LOC1 DEF_BIT_26 /* Local address match (Specific address 1 match). */
#define AT91RM9200_EMAC_RXBUF_STAT_UNK DEF_BIT_27 /* Unknown source address (reserved for future use). */
#define AT91RM9200_EMAC_RXBUF_STAT_EXT DEF_BIT_28 /* External address (optional). */
#define AT91RM9200_EMAC_RXBUF_STAT_UNI DEF_BIT_29 /* Unicast hash match. */
#define AT91RM9200_EMAC_RXBUF_STAT_MULTI DEF_BIT_30 /* Multicast hash match. */
#define AT91RM9200_EMAC_RXBUF_STAT_BCAST DEF_BIT_31 /* Global all ones broadcast address detected. */
/*
*********************************************************************************************************
* LOCAL FUNCTION PROTOTYPES
*********************************************************************************************************
*/
static void NetNIC_RxISR_Handler (void); /* ISR for RX interrupts. */
static void NetNIC_TxISR_Handler (void); /* ISR for TX interrupts. */
static void NetNIC_TxPktDiscard (NET_ERR *perr);
/* -------- AT91RM9200 EMAC FNCTS -------------------- */
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