📄 net_nic.c
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/*
*********************************************************************************************************
* uC/TCP-IP
* The Embedded TCP/IP Suite
*
* (c) Copyright 2003-2007; Micrium, Inc.; Weston, FL
*
* All rights reserved. Protected by international copyright laws.
*
* uC/TCP-IP is provided in source form for FREE evaluation, for educational
* use or peaceful research. If you plan on using uC/TCP-IP in a commercial
* product you need to contact Micrium to properly license its use in your
* product. We provide ALL the source code for your convenience and to help
* you experience uC/TCP-IP. The fact that the source code is provided does
* NOT mean that you can use it without paying a licensing fee.
*
* Network Interface Card (NIC) port files provided, as is, for FREE and do
* NOT require any additional licensing or licensing fee.
*
* Knowledge of the source code may NOT be used to develop a similar product.
*
* Please help us continue to provide the Embedded community with the finest
* software available. Your honesty is greatly appreciated.
*********************************************************************************************************
*/
/*
*********************************************************************************************************
*
* NETWORK INTERFACE CARD
*
* AT91RM9200 EMAC
*
* Filename : net_nic.c
* Version : V1.90
* Programmer(s) : JDH
*********************************************************************************************************
* Note(s) : (1) Supports EMAC section of Atmel's AT91RM9200 microcontroller as described in
*
* Atmel Corporation (ATMEL; http://www.atmel.com).
* (a) AT91RM9200 (ATMEL AT91RM9200; Revision 1768B-ATARM-08/03).
*
* (2) REQUIREs Ethernet Network Interface Layer located in the following network directory :
*
* \<Network Protocol Suite>\IF\Ether\
*
* where
* <Network Protocol Suite> directory path for network protocol suite
*
* (3) Since the AT91RM9200 EMAC (NIC) module is integrated into the AT91RM9200 microcontroller,
* the endianness of the registers is the same as the CPU, which is little-endian by default.
*********************************************************************************************************
*/
/*
*********************************************************************************************************
* INCLUDE FILES
*********************************************************************************************************
*/
#define NET_NIC_MODULE
#include <net.h>
/*
*********************************************************************************************************
* CONSTANTS
*********************************************************************************************************
*/
/* ----------- AT91RM9200 EMAC RX BUFFERS ------------ */
/* Buffer size MUST be divisible by 16 and MUST be */
#define AT91RM9200_EMAC_RX_BUF_SIZE 1536 /* greater than 1518 or 1522 (VLAN) bytes. */
#define AT91RM9200_EMAC_TX_BUF_SIZE 1536
#define AT91RM9200_EMAC_TX_NUM_BUFS 2
/*
*********************************************************************************************************
* DATA TYPES
*********************************************************************************************************
*/
typedef struct {
CPU_INT32U RxBufAddr; /* Address of RX buffer. */
CPU_INT32U RxBufStatus; /* Status of RX buffer. */
} AT91RM9200_EMAC_RX_BUF_HDR; /* See 'AT91RM9200 EMAC RECEIVE BUFFER DESCRIPTOR'. */
/*
*********************************************************************************************************
* CONSTANTS
*********************************************************************************************************
*/
/* Array of buffer descriptors. */
/* MUST be 16-word aligned (AT91RM9200 errata #11). */
static volatile AT91RM9200_EMAC_RX_BUF_HDR *AT91RM9200_EMAC_RxBufHdrs;
/* RX buffers. */
static volatile CPU_INT08U *AT91RM9200_EMAC_RxBuf;
/* TX buffer. */
static volatile CPU_INT08U *AT91RM9200_EMAC_TxBuf;
/* RX buffer currently fetched. */
static CPU_INT16U AT91RM9200_EMAC_RxBufNbr;
/* TX buffer currently fetched. */
static CPU_INT16U AT91RM9200_EMAC_TxBufNbr;
/*
*********************************************************************************************************
* AT91RM9200 EMAC REGISTERS
*
* Note(s) : (1) See ATMEL AT91RM9200, pages 573 - 591 for AT91RM9200 register summary.
*
* (2) Since the AT91RM9200 EMAC (NIC) module is integrated into the AT91RM9200 microcontroller,
* the indianness of the registers is the same as the CPU, which is little-endian by default.
*
* (3) Registers referenced as offsets from a base register address. The base register address
* MUST be correctly implemented in product-specific I/O functions NetNIC_Rd16() & NetNIC_Wr16().
* See ATMEL AT91RM9200, pages 31 - 33 for AT91RM9200 internal memory mapping.
*
* (4) Registers referenced as offsets from a base register address (see Note #2). The base register
* address MUST be correctly implemented in product-specific I/O functions NetNIC_Rd32() &
* NetNIC_Wr32(). See ATMEL AT91RM9200, pages 573 - 591 for AT91RM9200 register summary.
*
* (5) To protect AT91RM9200 register accesses during multi-thread operation, registers MUST be
* accessed in critical sections &/or mutual exclusion.
*
* (a) For single-register, single-access; critical sections are implemented in
* AT91RM9200_EMAC_RegRd & AT91RM9200_EMAC_RegWr().
*
* (b) For read-modify-write register access OR multiple-register-access sequences; critical
* sections &/or mutual exclusion enclosing the entire register access/sequence is REQUIRED.
*********************************************************************************************************
*/
/* -------- CONFIGURATION REGISTERS ------------------ */
#define AT91RM9200_REG_EMAC_CTL_OFFSET 0x00 /* EMAC Control Register */
#define AT91RM9200_REG_EMAC_CFG_OFFSET 0x04 /* EMAC Configuration Register */
#define AT91RM9200_REG_EMAC_SR_OFFSET 0x08 /* EMAC Status Register */
#define AT91RM9200_REG_EMAC_TAR_OFFSET 0x0C /* EMAC Transmit Address Register */
#define AT91RM9200_REG_EMAC_TCR_OFFSET 0x10 /* EMAC Transmit Control Register */
#define AT91RM9200_REG_EMAC_TSR_OFFSET 0x14 /* EMAC Transmit Status Register */
#define AT91RM9200_REG_EMAC_RBQP_OFFSET 0x18 /* EMAC Receive Buffer Queue Pointer */
#define AT91RM9200_REG_EMAC_RSR_OFFSET 0x20 /* EMAC Receive Status Register */
#define AT91RM9200_REG_EMAC_ISR_OFFSET 0x24 /* EMAC Interrupt Status Register */
#define AT91RM9200_REG_EMAC_IER_OFFSET 0x28 /* EMAC Interrupt Enable Register */
#define AT91RM9200_REG_EMAC_IDR_OFFSET 0x2C /* EMAC Interrupt Disable Register */
#define AT91RM9200_REG_EMAC_IMR_OFFSET 0x30 /* EMAC Interrupt Mask Register */
#define AT91RM9200_REG_EMAC_MAN_OFFSET 0x34 /* EMAC PHY Maintenance Register */
/* -------- STATISTIC REGISTERS ---------------------- */
#define AT91RM9200_REG_EMAC_FRA_OFFSET 0x40 /* Frames Transmitted OK Register */
#define AT91RM9200_REG_EMAC_SCOL_OFFSET 0x44 /* Single Collision Frame Register */
#define AT91RM9200_REG_EMAC_MCOL_OFFSET 0x48 /* Multiple Collision Frame Register */
#define AT91RM9200_REG_EMAC_OK_OFFSET 0x4C /* Frames Received OK Register */
#define AT91RM9200_REG_EMAC_SEQE_OFFSET 0x50 /* Frame Check Sequence Error Register */
#define AT91RM9200_REG_EMAC_ALE_OFFSET 0x54 /* Alignment Error Register */
#define AT91RM9200_REG_EMAC_DTE_OFFSET 0x58 /* Deferred Transmission Frame Register */
#define AT91RM9200_REG_EMAC_LCOL_OFFSET 0x5C /* Late Collision Register */
#define AT91RM9200_REG_EMAC_ECOL_OFFSET 0x60 /* Excessive Collision Register */
#define AT91RM9200_REG_EMAC_CSE_OFFSET 0x64 /* Carrier Sense Error Register */
#define AT91RM9200_REG_EMAC_TUE_OFFSET 0x68 /* Transmit Underrun Error Register */
#define AT91RM9200_REG_EMAC_CDE_OFFSET 0x6C /* Code Error Register */
#define AT91RM9200_REG_EMAC_ELR_OFFSET 0x70 /* Excessive Length Error Register */
#define AT91RM9200_REG_EMAC_RJB_OFFSET 0x74 /* Receive Jabber Register */
#define AT91RM9200_REG_EMAC_USF_OFFSET 0x78 /* Undersize Frame Register */
#define AT91RM9200_REG_EMAC_SQEE_OFFSET 0x7C /* SQE Test Error Register */
#define AT91RM9200_REG_EMAC_DRFC_OFFSET 0x80 /* Discarded RX Frame Register */
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