egaregs.txt

比较详尽的VGA端口寄存器的文档

3C0h:  Attribute Controller: Address register
bit 0-4  Address of data register to write to port 3C0h.
      5  If set screen output is enabled and the palette can not be modified,
         if clear screen output is disabled and the palette can be modified.


Port 3C0h is special in that it is both address and data-write register.
An internal flip-flop remembers whether it is currently acting as address or
data register. Accesses to the attribute controller must be separated by at
least 250ns. Reading port 3dAh will reset the flip-flop to address mode.


3C0h index 0-Fh  (W):  Attribute: Palette
bit   0  Primary Blue
      1  Primary Green
      2  Primary Red
      3  Secondary Blue
      4  Secondary Green
      5  Secondary Red

3C0h index 10h (W):  Attribute: Mode Control Register
bit   0  Graphics mode if set, Alphanumeric mode else.
      1  Monochrome mode if set, color mode else.
      2  9-bit wide characters if set.
         The 9th bit of characters C0h-DFh will be the same as
         the 8th bit. Otherwise it will be the background color.
      3  If set Attribute bit 7 is blinking, else high intensity.

3C0h index 11h (W):  Attribute: Overscan Color Register.
bit 0-5  Color of screen border. Color is defined as in the palette registers.
Note: The EGA requires the Overscan color to be 0 in high resolution modes.

3C0h index 12h (W):  Attribute: Color Plane Enable Register
bit   0  Bit plane 0 is enabled if set.
      1  Bit plane 1 is enabled if set.
      2  Bit plane 2 is enabled if set.
      3  Bit plane 3 is enabled if set.
    4-5  Video Status MUX. Diagnostics use only.
         Two attribute bits appear on bits 4 and 5 of the Input Status
         Register 1 (3dAh).  0: Red/Blue, 1: Blue(I)/Green, 2: Red(I)/Green(I)

3C0h index 13h (W):  Attribute: Horizontal PEL Panning Register
bit 0-3  Indicates number of pixels to shift the display left
         Value  9bit textmode   256color mode   Other modes
           0          1               0              0
           1          2              n/a             1
           2          3               1              2
           3          4              n/a             3
           4          5               2              4
           5          6              n/a             5
           6          7               3              6
           7          8              n/a             7
           8          0              n/a            n/a

3C2h (R):  Input Status #0 Register
bit   4  Status of the switch selected by the Miscellaneous Output
         Register 3C2h bit 2-3. Switch high if set.
      5  Pin 19 of the Feature Connector (FEAT0) is high if set
      6  Pin 17 of the Feature Connector (FEAT1) is high if set
      7  If set IRQ 2 has happened due to Vertical Retrace. Should be cleared
         by IRQ 2 interrupt routine by clearing port 3d4h index 11h bit 4.

3C2h (W):  Miscellaneous Output Register
bit   0  If set Color Emulation. Base Address=3Dxh else Mono Emulation. Base
         Address=3Bxh.
      1  Enable CPU Access to video memory if set
    2-3  Clock Select. 0: 14MHz, 1: 16MHz, 2: External
      4  Disable internal video drivers if set
      5  When in Odd/Even modes Select High 64k bank if set
      6  Horizontal Sync Polarity. Negative if set
      7  Vertical Sync Polarity. Negative if set
         Bit 6-7 indicates the number of lines on the display:
           0: 200 lines, 2: 350 lines
Note: Set to all zero on a hardware reset.

3C4h index  0  (W):  Sequencer: Reset
bit   0  Asynchronous Reset if clear
      1  Synchronous Reset if clear

3C4h index  1  (W):  Sequencer: Clocking Mode
bit   0  If set character clocks are 8 dots wide, else 9.
      1  If set the CRTC uses 2/5 of the clock cycles, else 4/5.
      2  If set loads video serializers every other character
         clock cycle, else every one.
      3  If set the Dot Clock is Master Clock/2, else same as Master Clock
          (See 3C2h bit 2-3). (Doubles pixels).

3C4h index  2  (W):  Sequencer: Map Mask Register
bit   0  Enable writes to plane 0 if set
      1  Enable writes to plane 1 if set
      2  Enable writes to plane 2 if set
      3  Enable writes to plane 3 if set

3C4h index  3  (W):  Sequencer: Character Map Select Register
bit 0-1  Selects EGA Character Map (0..3) if bit 3 of the character
         attribute is clear.
    2-3  Selects EGA Character Map (0..3) if bit 3 of the character
         attribute is set.
Note: Character Maps are placed as follows:
      Map 0 at 0k, map 1 at 16k, map 2 at 32k and map 3 at 48k

3C4h index  4  (W):  Sequencer: Memory Mode Register
bit   0  Set if in an alphanumeric mode, clear in graphics modes.
      1  Set if more than 64kbytes on the adapter.
      2  Enables Odd/Even addressing mode if set. Odd/Even mode places all odd
         bytes in plane 1&3, and all even bytes in plane 0&2.

3CAh (W):  Graphics 2 Position
bit 0-1  Select which bit planes should be controlled by Graphics Controller
         #2. Always set to 1.

3CCh (W):  Graphics 1 Position
bit 0-1  Select which bit planes should be controlled by Graphics Controller
         #1. Always set to 0.

3CEh index  0  (W):  Graphics: Set/Reset Register
bit   0  If in Write Mode 0 and bit 0 of 3CEh index 1 is set a write to
         display memory will set all the bits in plane 0 of the byte to this
         bit, if the corresponding bit is set in the Map Mask Register (3CEh
         index 8).
      1  Same for plane 1 and bit 1 of 3CEh index 1.
      2  Same for plane 2 and bit 2 of 3CEh index 1.
      3  Same for plane 3 and bit 3 of 3CEh index 1.

3CEh index  1  (W):  Graphics: Enable Set/Reset Register
bit   0  If set enables Set/reset of plane 0 in Write Mode 0.
      1  Same for plane 1.
      2  Same for plane 2.
      3  Same for plane 3.

3CEh index  2  (W):  Graphics: Color Compare Register
bit 0-3  In Read Mode 1 each pixel at the address of the byte read is compared
         to this color and the corresponding bit in the output set to 1 if
         they match, 0 if not. The Color Don't Care Register (3CEh index 7)
         can exclude bitplanes from the comparison.

3CEh index  3  (W):  Graphics: Data Rotate
bit 0-2  Number of positions to rotate data right before it is written to
         display memory. Only active in Write Mode 0.
    3-4  In Write Mode 2 this field controls the relation between the data
         written from the CPU, the data latched from the previous read and the
         data written to display memory:
           0: CPU Data is written unmodified
           1: CPU data is ANDed with the latched data
           2: CPU data is ORed  with the latch data.
           3: CPU data is XORed with the latched data.

3CEh index  4  (W):  Graphics: Read Map Select Register
bit 0-1  Number of the plane Read Mode 0 will read from.

3CEh index  5  (W):  Graphics: Mode Register
bit 0-1  Write Mode: Controls how data from the CPU is transformed before
         being written to display memory:
           0: Mode 0 works as a Read-Modify-Write operation.
              First a read access loads the data latches of the EGA with the
              value in video memory at the addressed location. Then a write
              access will provide the destination address and the CPU data
              byte. The data written is modified by the function code in the
              Data Rotate register (3CEh index 3) as a function of the CPU
              data and the latches, then data is rotated as specified by the
              same register.
           1: Mode 1 is used for video to video transfers.
              A read access will load the data latches with the contents of
              the addressed byte of video memory. A write access will write
              the contents of the latches to the addressed byte. Thus a single
              MOVSB instruction can copy all pixels in the source address byte
              to the destination address.
           2: Mode 2 writes a color to all pixels in the addressed byte of
              video memory. Bit 0 of the CPU data is written to plane 0 et
              cetera. Individual bits can be enabled or disabled through the
              Bit Mask register (3CEh index 8).
      2  Forces all outputs to a high impedance state if set.
      3  Read Mode