ati.txt

比较详尽的VGA端口寄存器的文档

   ATI Technologies Super VGA Chip Sets.

    18800              V3. ROM BIOS label: V3M
    18800-1    100pin  V4. ROM BIOS label: V4M
    18800-1    100pin  V5. Uses 18810 Dot Clock Chip. ROM BIOS label: V5M
    28800-2            V6. VGA Wonder+
    28800-4            V7. VGA Wonder XL
    28800-5            VGA Wonder (1MB)/XL, Graphics/Ultra (VGA chip)
    28800-6    160pin  VGA Wonder XL24
    38800-1            Mach 8.  8514/Ultra and Graphics/Ultra (8514/A chip)
    68800-3    208pin  Mach 32. Graphics Ultra Pro/+ Combined 8514/A and
                          VGA chip.
    68800-6    208pin  As -3, but with memory mapped registers
    68800-LX   208pin  As -6, but only supports DRAM (no VRAM)
    68800-AX   208pin  As -6, but supports PCI bus
    88800GX    208pin  Mach64 (there is also an 88800CX ??)

Support chips:
ATI18810  Clock chip for 18800-1, 28800
ATI18811  Clock chip for 68800
ATI18820  Bus Mouse Controller

    ATI Prism Elite uses Trident 8800CS chips.

    ATI VGA Wonder XL can use the Sierra HiColor RAMDAC.

Note that the base register for the ATI extended registers should be read from
the word at 0C000h:10h (NOT on Mach64), as ATI reserves the right to change
the base address. However all current implementations use 1CEh.

Note:  The ATI chips handles the indexed registers slightly differently
       from other VGA chips, as the index register must be written before
       each read or write of the associated data register.


1CEh index 80h (R/W):  ATI Register 0 (ATI00)                     (68800 only)
bit  0-7  Scratch Pad

1CEh index 81h (R/W):  ATI Register 1 (ATI01)                     (68800 only)
bit  0-7  Scratch Pad

1CEh index 82h (R/W):  ATI Register 2 (ATI02)                     (68800 only)
bit  0-7  Scratch Pad

1CEh index 83h (R/W):  ATI Register 3 (ATI03)                     (68800 only)
bit  0-7  Scratch Pad

1CEh index 84h (R/W):  ATI Register 4 (ATI04)                     (68800 only)
bit  0-7  Scratch Pad

1CEh index 85h (R/W):  ATI Register 5 (ATI05)                     (68800 only)
bit  0-3  CPUCLK Select. Selects the number of CPU clocks for the basic
          command cycle in the local bus.
     4-5  Delay Memory Read Ready Control.
           0: Read Ready signal is 1 MCLK before memory data is available
           1: Read Ready signal is simultaneously with the memory data.
           2: Read Ready signal is 1 MCLK after memory data is available
           3: Read Ready signal is 2 MCLKs after memory data is available
       6  Delay latch memory read data by one half memory clock cycle in VGA
          planar mode.
       7  Cursor Blink Rate Select. Half normal rate if set.

1CEh index 86h (R/W):  ATI Register 6 (ATI06)                     (68800 only)
bit  0-2  Text mode character FIFI depth
     4-6  Number of CPUCLK cycles in the local bus BIOS ROM read cycle.

1CEh index A0h (R/W):  ATI Register 20 (ATI20)                       (28800 +)
bit  0-3  (68800 only) Display FIFO. Selects the video FIFO depth where the
           Display Request changes from low to high priority in the memory
           controller. Default is 8
       4  Enable 16bit ROM if set
     5-6  (68800 only) RAMDAC Extended Address Select. Connected to RS2 and
           RS3 on the RAMDAC, giving access to all 8 or 16 registers on
           advanced RAMDACs.

1CEh index A1h (R/W):  ATI Register 01h                              (28800 +)
bit  0-2  Reserved
     3-4  Digital Monitor Detection
     5-7  Reserved

1CEh index A2h (R/W):  ATI Register 02h                              (28800 +)
bit  0-7  Reserved

1CEh index A3h (R/W):  ATI Register 23 (ATI23)                       (28800 +)
bit  0-2  16bit ROM Access. ROM access time (Single 16bit ROM).
       3  Cursor Start Address bit 17. Bit 17 of the Cursor Start Address
           (3d4h index 0Eh,0Fh) Bit 16 is in
       4  Display start address bit 17. Bit 17 of the Display Start Address
           (3d4h index 0Ch,0Dh). Bit 16 is in 1CEh index B0h bit 6.
     5-7  Reserved

1CEh index A4h (R/W):  ATI Register 24 (ATI24)                       (28800 +)
bit  0-3  ROM page 0
     4-7  ROM page 1

1CEh index A5h (R/W):  ATI Register 25 (ATI25)                       (28800 +)
bit  0-3  ROM page 2
     4-7  ROM page 3

1CEh index A6h (R/W):  ATI Register 26 (ATI26)                       (28800 +)
bit    0  (68800) Display Enable Skew-by-2. If set skews the "Display Enable"
            signal by 2 character clocks.
       3  (68800) General Purpose R/W Bit.
       6  (68800) Solid Underline. Set for solid underline in monochrome text,
            clear for dashed underline.
       7  Forced read 3CCh. If set forces GENMO[1-7] to 0 while reading 3CCh

1CEh index A7h (R/W):  ATI Register 07h                              (28800 +)
bit    0  Enable True color mode
     1,3  True Color DAC installed
       2  Reserved
     4-5  Forced pixel data to high
       6  Skew display enable
       7  Enable divide by 3 clock

1CEh index A8h (R):  ATI Register 28 (ATI28)                     (28800-5 +)
bit  0-1  Vertical Line Counter bit 8-9
     2-7  Reserved

1CEh index A9h (R):  ATI Register 29 (ATI29)                     (28800-5 +)
bit  0-7  Vertical Line Counter bit 0-7
Note: The VGA Wonder documents A8h as the low byte and A9h as the high byte,
      but at least for the 28800-6 and Mach32 A8h IS the low byte.

1CEh index AAh (R/W):  ATI Register 0Ah                            (28800-5 +)
bit  0-3  (R) Chip Revision ID. 6 for the 28800-6, (5 for the 28800-5 ??)
       4  Address/Data bus configuration
     5-7  Reserved

1CEh index ABh (R/W):  ATI Register 2B (ATI2B)                       (28800 +)
bit    0  Video Zero Wait-State Enable. Enables zero wait state support for
          video memory write if set
       1  BIOS Zero Wait-State Enable. Enables zero wait state for BIOS read
          if set
       2  (68800) I/O Zero Wait State Enable if set
       3  Select secondary display
          (68800) Double Scan Lock Enable. Locks 3d4h index 9 bit 7 if set
       4  (28800-6 +) Lock DAC write. If set locks the RAMDAC write signal
       5  (28800-6) Zero wait state enable
       6  Restrict CPU access
          (68800) Memory Data Delay Latch in Text Mode. If set latching of
           memory data from the DRAM port is delayed by 1/2 MCLK in text modes
       7  Video Data Delay Latch in Text Mode. If set internal latching of
          video data from the serial port is delayed by 1/2 MCLK in text modes

1CEh index ACh (R/W):  ATI Register 0Ch                            (28800-6 +)
bit    0  Enable Linear Addressing
     1-5  Reserved
       6  Enable 1024x768x16 color planar pass through internal palette
       7  Reserved

1CEh index ADh (R/W):  ATI Register 2D (ATI2D)                     (28800-6 +)
bit    0  (28800-6) Extended Horizontal Total bit 8. Bits 0-7 are in 3d4h
             index 0. Only used if bit 3 is set
       1  (28800-6) Extended CRTC Start Blanking bit 8. Bits 0-7 are in 3d4h
             index 2. Only used if bit 3 is set
     0-1  (68800) Extended Cursor Address. Bits 18-19 of the Cursor Address
           register (3d4h index 0Eh,0Fh). Bit 16 is in 1CEh index B0h bit 2
           and bit 17 in 1CEh index A3h bit 3.
       2  (28800-6) Extended CRTC Horizontal Retrace Start bit 8. Bits 0-7 are
           in 3d4h index 4. Only used if bit 3 is set
       3  (28800-6) Extended CRTC Registers Enable
     2-3  (68800) Extended Start Address. Bits 18-19 of the Display Start
           Address register (3d4h index 0Ch,0Dh). Bits 16 is in 1CEh index B0h
           bit 6 and bit 17 in 1CEh index A3h bit 4
     4-7  Extended Character Map Address. Bits 16-19 of the address where the
          font maps are stored. See 3C4h index 3.

1CEh index AEh (R/W):  ATI Register 2E (ATI2E)                  (68800 only?)
bit  0-1  (68800) Write/Single bank bit 4-5
     2-3  (68800) Read bank bit 4-5
       4  If sets locks the CPUCLK select bits (1CEh index 85h bits 0-3).
     5-7  Horizontal Sync Skew relative to pixel clock.

1CEh index AFh (R/W):  ATI Register 0Fh
bit  0-7  Reserved

1CEh index B0h (R/W):  ATI Register 30 (ATI30)
bit    0  Skews Display Enable by one character clock if set
       1  (188xx) Enable 256 color modes
          (288xx) Enable alt Video memory organization in text modes
       2  (188xx) Enable 256 color modes
          (28800 +) Extended Cursor Start Address. Bit 16 of the Cursor Start
           Address register (3d4h index 0Eh,0Fh). Bit 17 is in 1CEh index A3
           bit 3.
       3  (188xx) Enable 8 CRT accesses for each CPU access
     3-4  (28800-4 +) Video memory: 0=256k, 1=1M, 2=512K
       4  (28800-2) Video memory: 0=256k, 1=512k
       5  (28800 +) ATI-Ext 256 Color Mode Select. Enables extended 256 color
            modes if set
     6-7  (188xx) Display Start Address bit 16-17
       6  (28800 +) Extended Display Start Address. Bit 16 of the Display
           Start Address register (3d4h index 0Ch,0Dh). Bit 17 is in 1CEh
           index A3h bit 4
       7  (28800 +) Enable Higher bandwidth in VRAM

1CEh index B1h (R/W):  EGA Compatibility and Double Scanning Enable
bit    0  EGA I/O Address Compatibility. Forces all VGA I/O addresses to be
          EGA compatible if set
       1  EGA Register Compatibility. Forces all VGA registers to be EGA
          compatible if set
       2  General purpose read/write bit
     3-5  Scan Function. Double scanning/3 of 4 scanning enable
            0: Normal
            1: Enable double scanning in graphics mode
            2: Enable 3 of 4 scanning in graphics mode
            5: Enable double scanning in text mode
            6: Enable 3 of 4 scanning in text mode
       6  Vertical Timings Divide by 2. If set divides the Vertical timing
          parameters by 2
       7  Reserved

1CEh index B2h (R/W):  Memory Page Select
bit    0  (18800) Enable interlace if set
          (18800-1) reserved
          (28800 +) Read bank no bit 3
     1-3  (18800-1) Write/Single bank no.
     1-4  (28800 +) Write/Single bank no
          (18800) Bank no. in 64 chunks
       5  (18800) Enable internal DIP switch settings (EGA mode)
       6  (18800) External clock select. Bit 2 of the clock select. Bits 0-1
            are in 3C2h/3CCh bits 2-3. Clocks in MHz:
             0: 50.175, 1: 56.644, 3: 44.900, 4: 44.900, 5: 50.175, 7: 36.000
       7  (18800) Reserved
     5-7  (18800-1 +) Read bank no

1CEh index B3h (R/W):  ATI Register 33 (ATI33)
bit    0  EEPROM data input
       1  EEPROM clock source
       2  Enable EEPROM interface
       3  EEPROM chip select. Enables EEPROM if set
       4  (18800?)  Enable PS/2 decoding
          (18800-1) Disable memory beyond 256K if set
       5  (28800 +) XOR with input status bit HSYNC to select 8 or 16 bit
                    video memory operation
          (68800) ISA bus 8/16bit Video Memory Operation. Selects 8 or 16 bit
           Video memory operation depending on whether input pin RMCE1B is
           grounded through a 2K Ohm resistor.
           If grounded:      1:  8bit, 1: 16bit
           If NOT grounded:  0: 16bit, 1:  8bit
       6  (18800) Enable 1 CRT access to 1 CPU access
          (18800-1 +)  4bit PEL, 1bit/map. Enables 1024x768 16 color planar
            pixel mode if set. If set 16 pixels are loaded and displayed per
            character clock rather than the normal 8, also the CRTC offset
            register (3d4h index 13h) is in units of 4 bytes rather than 2.
       7  Double Scan Enable. Enable double scanning for 200 line modes if set
Note: This register should not be modified on revision 1 chips.

1CEh index B4h (R/W):  Emulation Control
bit    0  Enable CGA emulation if set
       1  Enable Hercules emulation if set
       2  Write Protect CRT09[0-4,7]. If set write protects 3d4h index 9 bits
           0-4 and 7