video7.txt

比较详尽的VGA端口寄存器的文档

  Video 7 Super VGA.
  Bought by Headland Technologies in
  Bought by SPEA Software AG in 1993.

The earliest V7/Headland boards use Chips&Technologies and Cirrus chips.


G2 GC205   VRAM-I/VGA-16 boards ?. Also known as HT 208 rev 1-3 ??
G2 GC208   V7 1024i boards. Also known as HT208. Split banks
HT 209     V7VRAM-II boards
HT 216     Color expansion. RAster ops.
HT 216-32  Local bus version of HT216 ?


Board:      Chip:                     Features:

VGA-16
VRAM I                                Hardware Cursor
VRAM II     HT-208 rev B,C or D       Split Bank
VGA16       HT-216
1024i       HT-216



100h (R/W?): Microchannel ID low
bit 0-7  Card ID bit 0-7

101h (R/W?): Microchannel ID high
bit 0-7  Card ID bit 8-15

102h (R/W): Alt Video Subsystem Enable
bit 0  Enable Video if set. Must be armed by 3C4h index 0FCh bit 7
       or in setup mode (46E8h bit4) to change.

3C2h (W): Misc Output register
bit 5  Bit 1 of Bank no.
Note:  This register can be read at 3CCh.

3C3h (R/W): Video Subsystem Enable
bit 0  Enable Microchannel Video if set
       Must be armed by 3C4h index 0FCh bit 7 to change.

3C4h index  6  (R/W):  Extension Control
bit   0  (R) Extensions enabled if set
bit 0-7  (W) 0EAh Enables extensions, 0AEh disables.

3C4h index  7  (R/W):  Reset Horizontal Character Counter

3C4h index  Bh (R/W):  CA1 ??
bit   0  If set the CA1 port is an output with the state  from bit 1,
         if clear the port is an input. The state is returned in bit 1.
      1  Data pin for CA1. Usually connected to 8/6 pin on DAC
Note: Some sort of access to index 0D0h is needed to enable the port.

3C4h index 80h (R/W):  Test

3C4h index 81h (R/W):  Test

3C4h index 82h (R/W):  Test

3C4h index 83h (R/W):  Attribute Control Index

3C4h index 8Eh W(R):  Chip Version
bit 0-15  Chip version. Index 8Fh is the major version, and 8Eh is the minor.
          Originally this was probably for two different chips.
            8xxxh-FFFFh  VEGA VGA Chip
                  70xxh  HT208 chip rev. 1,2 or 3 (VRAM I/VGA-16)
                  7070h  G2 GC205
                  714xh  HT208 chip rev A (VRAM II ?). Also G2 GC208.
                  7151h  HT208 chip rev B (VRAM II)
                  7152h  HT208 chip rev C or D (VRAM II)
                  7760h  HT216 rev B or C
                  7763h  HT216 rev B, C or D  (huh ??)
                  7764h  HT216 rev E
                  7765h  HT216 rev F

3C4h index 94h (R/W):  Pointer Pattern Address
bit 0-7  Start address of the Pointer Pattern. This value selects the 256 byte
         block within the last 64k of the 256k block selected by index 0FFh
         bits 5-6.
         The cursor map consists of two 32x32 bitmaps. The first is the AND
         mask and the second is the XOR mask.
            AND     XOR
             0       0      Black
             0       1      Inverse screen data
             1       0      Screen data
             1       1      White

3C4h index 9Ch (R/W):  Pointer Horizontal Position High
bit 0-2  Bit 8-10 of the X co-ordinate of the Cursor

3C4h index 9Dh (R/W):  Pointer Horizontal Position Low
bit 0-7  Bit 0-7 of the X co-ordinate of the Cursor

3C4h index 9Eh (R/W):  Pointer Vertical Position High
bit 0-1  Bit 8-9 of the Y co-ordinate of the Cursor

3C4h index 9Fh (R/W):  Pointer Vertical Position Low
bit 0-7  Bit 0-7 of the Y co-ordinate of the Cursor

3C4h index A0h (R/W):  GC Memory Latch 0
bit 0-7  Plane 0 Memory Latch Data

3C4h index A1h (R/W):  GC Memory Latch 1
bit 0-7  Plane 1 Memory Latch Data

3C4h index A2h (R/W):  GC Memory Latch 2
bit 0-7  Plane 2 Memory Latch Data

3C4h index A3h (R/W):  GC Memory Latch 3
bit 0-7  Plane 3 Memory Latch Data

3C4h index A4h (R/W):  Clock Select
bit 2-4  Clock select bit 0-2. Bit 3 is in index F8h bit 0
         This is activated when 3C2h is written. Actually 3C2h/3CCh bits 2-3
         will override bits 2-3 of this register
         HT208-A (in MHz) generates:
           0: 25.175,   1: 48.6,    2: 22.9,    3: 0
           4: 34,       5: 48.6,    6: 22.9,    7: 0
           8: 25.175,   9: 28.322, 10: 22.9,   11: 0
          12: 34,      13: 36,     14: 22.9,   15: 40
         Another card gives (8-15 unknown):
           0: 25.175,   1: 28.322,  2: 30.000,  3: 32.514
           4: 34.000,   5: 36.000,  6: 38.000,  7: 40.000

3C4h index A5h (R/W):  Cursor Attributes
bit 0  Cursor blink enabled if clear
    3  Text Cursor Mode is XOR if set, Replace if clear
    7  Hardware Graphics Cursor Enabled if set

3C4h index B3h (R/W):  Scratch RAM
bit 0-7  Scratch

3C4h index B4h (R):  Power On Reset 0                                  (HT216)

3C4h index B5h (R):  Power On Reset 1                                  (HT216)

3C4h index B6h (R):  Power On Reset 2                                  (HT216)

3C4h index B7h (R):  Power On Reset 3                                  (HT216)

3C4h index C0h (R/W):  Monochrome Lock

3C4h index C1h (R/W):
bit   0  Set to enable 8bit DAC rather than 6bit.

3C4h index C8h (R/W):  Miscellaneous Control 2
bit   0  Set to enable MOVSB operation ??                        (HT216 only?)
      4  Set in Extended 256 color modes
      6  Enable Linear Addressing if set

3C4h index C9h (R/W):  Extended Linear Address Offset
bit 0-3  Bits 20-23 of the Linear Address Offset

3C4h index CAh (R/W):  Horizontal Overflow                             (HT216)

3C4h index CBh (R/W):  Low Water Mark                                  (HT216)

3C4h index CCh (R/W):  DM Function Control                             (HT216)

3C4h index CDh (R/W):  Extended ALU Function Control                   (HT216)
bit 0-1  Color Expansion mode:
          0,2: VGA compatible mode
            1: Packed pixel 8plane color expansion
            3: Planar color expansion mode
    2-3  Bit mask source. 0: Bitmask from 3CEh index 8
           1: Bit mask from CPU byte, 2,3: Bit mask from 3C4h index F5h
      5  If set RMW cycles are enabled.
      6  If set enables Source to Destination alignment.
      7  Set to Enable Raster Operations

3C4h index CEh (R/W):  Extended ALU Function Select                    (HT216)
bit 0-3  Raster Operation.
             0: Set to 0  ...

3C4h index CFh (R/W):  Extended Linear Address Offset High             (HT216)
bit 0-7  Bits 24-31 of the Linear Address Offset

3C4h index E0h (R/W):  Miscellaneous Control                   (HT208 rev A +)
bit   0  Interlaced
    5-6  Reserved
      7  Enables Split Bank Mode if set(VRAM II or HT216 only)
         On the HT208 rev A, split banks appears to cause index E8h to be the
         read/write bank register for A000h-A7FFh and index E9h to be the
         read/write bank register for A800h-AFFFh.

3C4h index E1h (R/W):  Interlace Value

3C4h index E2h (R/W):  Extended Character Width Enable

3C4h index E3h (R/W):  High Water Mark

3C4h index E8h (R/W):  Single/Write Bank Register              (HT208 rev A +)
bit 0-7  Single/Write Bank in units of 4KB.
         For 16color modes this is in units of 1KB.

3C4h index E9h (R/W):  Read Bank Register                      (HT208 rev A +)
bit 0-7  Read Bank in units of 4KB.
         Only Active if Split mode enabled (3C4h index E0h bit 7 set)

3C4h index EAh (W): Switch Strobe
Note:  A write to this register copies the switch positions to
       the Switch Readback Register (3C4h index F7h).

3C4h index EBh (R/W):  Emulation Control

3C4h index ECh (R/W):  Foreground Latch 0
bit 0-7  Foreground Latch for plane 0. When in Dither Foreground mode
         (3C4h index FEh bit 2-3 = 2) the data in this register
         replaces the data written from the processor.

3C4h index EDh (R/W):  Foreground Latch 1
bit 0-7  Foreground Latch for plane 1.

3C4h index EEh (R/W):  Foreground Latch 2
bit 0-7  Foreground Latch for plane 2.

3C4h index EFh (R/W):  Foreground Latch 3
bit 0-7  Foreground Latch for plane 3.

3C4h index F0h (R/W):  Fast Foreground Latch Load
bit 0-7  The Foreground Latches (3C4h index ECh to EFh) for the four memory
         planes can be loaded by writing to this register. The writes will
         cycle through planes 0-3. A read will restart at plane 0.

3C4h index F1h (R/W):  Fast Latch Load State
bit 0-1  Background Latch Load State. Determines which of the four memory
         latches will be loaded by a write to 3C4h index F2h. Each write to
         index F2h will increment this value and each read from index F2h
         will reset it to 0.
    2-3  Unused
    4-5  Foreground Latch Load State. Determines which of the four Foreground
         latches (3C4h index ECh to EFh) will be loaded by the next write to
         3C4h index F0h. Each write to index F0h will increment this value
         and each read from index F0h will reset it to 0.
    6-7  Unused

3C4h index F2h (R/W):  Fast Background Latch Load
bit 0-7  The Memory Data Latches for the four memory planes can be loaded by
         writing to this register. The writes will cycle through planes 0-3.
         A read will restart at plane 0.

3C4h index F3h (R/W):  Masked Write Control   (Only with VRAM)
bit   0  Enables Masked Writes if set
      1  If set rotated CPU byte is used as WriteMask, else Masked Write Mask
         register is used.

3C4h index F4h (R/W):  Masked Write Mask      (Only with VRAM)
bit 0-7  If Masked Writes enabled (3C4h index F3h bit 0 set)
         Only the bits set here will be updated in Video memory.