📄 oak.txt
字号:
first (low bits) and the red last, if clear red comes first.
5-6 Bits/pixel. 0: 8bpp, 1: 16bpp, 2: 24bpp, 3: 32bpp
3DEh index 80h W(R/W): HC/HW Horizontal Position Start
3DEh index 82h W(R/W): HC/HW Vertical Position Start
3DEh index 84h (R/W): HC Horizontal Preset/HW Width Low
bit 0-5 (HC)
0-7 (HW) Low 8bits of the HW width. Upper bits are in index 85h
3DEh index 85h (R/W): HW Width High
bit 0-? High bits of the HW width. Low bits are in index 84h. This value is
the number of doublewords (4bytes) in each line.
3DEh index 86h (R/W): HC Vertical Preset Low/HW Height Low
3DEh index 87h (R/W): HW Height High
3DEh index 88h 3(R/W): HC Start Address
3DEh index 8Ch 4(R/W): HC Color 0
bit 0-31 Cursor color 0. Same format as the current display
3DEh index 90h 4(R/W): HC Color 1
bit 0-31 Cursor color 1. Same format as the current display
3DEh index 94h (R/W): HC Control Register
bit 0 Enable Hardware Cursor (HC) if set
1 HC display is over overscan if set, under if clear
2 HC Data format. Motorola if set, Intel if clear
3 HC Blink enabled if set
4-5 Blink Rate. 0: 4frames on+off, 1: 8f, 2: 16f, 3: 32f
3DEh index 96h (R/W): HW Control
bit 0 Select Hardware Window (HW) or Hardware Cursor (HC). 0: HC, 1: HW
1-2 Horizontal Scaling Factor. 0: None, 1: /2, 2: /4, 3: /8
3-4 Vertical Scaling Factor. 0: None, 1: /2, 2: /4, 3: /8
5 Select odd/even lines for scaling. 0: even, 1: odd
6 YUV or RGB for scaling. 0: data from Multimediaport is YUV, 1: RGB
7 Enable Mask Map for Multimedia Port
3DEh index 98h 3(R/W): HW Mask Map Start
3DEh index 9Ch 3(R/W): HW Start Address
3DEh index 9Fh (R/W): HW Address Offset
3DEh index F0h (R/W): Scratch Register 0
3DEh index F1h (R/W): Scratch Register 1
3DEh index F2h (R/W): Scratch Register 2
3DEh index F3h (R/W): Scratch Register 3
3DEh index F4h (R/W): Scratch Register 4
3DEh index F5h (R/W): Scratch Register 5
3DEh index F6h (R/W): Scratch Register 6
3DEh index F7h (R/W): Scratch Register 7
2x00h W(R): Vendor ID
bit 0-15 104Eh for Oak
2x02h W(R): Device ID
bit 0-15 0107h for the Oak-107
2x04h W(R/W): System Bus Command Register
bit 0 I/O Space. If set the device is allowed to respond to I/O accesses.
1 Memory Space. If set the device is allowed to respond to memory
accesses.
3 Special Cycle. If set the device is allowed to monitor special
cycles.
5 VGA Palette Snoop. Clear for normal DAC operation, set to enable
special DAC snoop mode where the DAC does not respond to writes.
6 Parity Error. If set the device responds to parity errors, if clear
ignores them.
7 Wait Cycle Control. If set enables address/data stepping.
8 System Error Driver. If set the Error driver reports address parity
errors, if clear it is disconnected.
9 Back to Back Cycle. If set there is no delay between bus cycles.
2x??h W(R): System Bus State
bit 7 (R) Fast back-to-back. Fast back-to-back supported if set
8 Bus Master
9-10 (R) Device Select Timing. Timing of DEVSEL#. 0: fast, 1: medium,
2: slow
11 Device Target-abort. Set if the VGA issues a target abort
12 Received Target-abort. Set if the VGA as master receives a target
abort.
13 Master Abort Status. Set if the VGA as master issues a master abort.
2x08h (R): Revision ID
2x??h D(): Class Code Register
bit 0-23 0 for non-VGA devices, 30000h for VGA compatible devices ??
2x??h (R): Programming Interface
2x??h (R/W): Cache Line Size
2x??h (R): Header Type
2x??h (R/W): Built-In Self Test
2x10h D(R/W): Memory Mapped I/O Base Address
bit 0 (R) Memory or I/O. 0: Memory mapped, 1: I/O mapped
1-2 (R) Locatable area. 0: Anywhere in 32bit address space, 1: Below
1MB, 2: anywhere in 64bit address space.
3 (R) Pre-fetchable. Set if memory is cacheable, clear if not.
4-7 (R) Address space size. 0: 256 bytes
8-31 Memory-Mapped I/O Base. Upper 24bits of the base address
2x14h D(R/W): Graphics Memory Base Address
bit 0 (R) Memory or I/O. 0: Memory mapped, 1: I/O mapped
1-2 (R) Locatable area. 0: Anywhere in 32bit address space, 1: Below
1MB, 2: anywhere in 64bit address space.
3 (R) Pre-fetchable. Set if memory is cacheable, clear if not.
4-19 (R) Address space size. 0: >= 1MB
20-22 (PCI) (R) Address block size. Always 0
20-22 (VL,ISA) Address block size. Bits 20-22 of the Base address
23-31 Base Address. Upper 9 bits of the base address.
2x??h D(R/W): Extended I/O Base Address
bit 0 (R) Memory or I/O. 0: Memory mapped, 1: I/O mapped
3 (R) Pre-fetchable. Set if memory is cacheable, clear if not.
4-7 (R) Address space size. 0: 256bytes
8-31 Base Address. Upper 24 bits of the base address.
2x30h (R/W): BIOS ROM Base Address
bit 0 (R/W) BIOS ROM Decode enabled if set
11-14 (R) ROM BIOS Min Size. If clear ROM BIOS is min. 32K
15-17 ROM BIOS size. Bits 15-17 of the base address. Depending on the size
of the ROM (see Configuration Register 2 - 3DEh index 8 bits 3-4)
some of these bits may be Read only and 0.
3DEh index 8 bits 3-4: Bit15 Bit16 Bit17 ROM Size:
0 R/W R/W R/W 32K
1 R/W R/W R(0) 64K
2 R/W R(0) R(0) 128K
3 R(0) R(0) R(0) 256K
18-31 ROM BIOS Address. Upper 14 bits of the base address.
2x3Ch (R/W): Interrupt Line
2x??h (R): Interrupt Pin
2x??h (R): Minimum Grant
2x??h (R): Maximum Latency
M+10h (R/W): Co-Processor Status
bit 0-1 (R) Map that needs data next. 0: Pattern, 1: Mask, 2: Source, 3: Dest
2 If set the map writing, if clear reading
3 (R) Map Status Valid
4 If set increase address for next access, if clear reset to map start
5 If set advance to next line, if clear stay on current line
7 (R) Co-Processor busy if set
M+11h (R/W): Co-Processor Control
bit 0 Select CINT interrupt source. VGA interrupt or Co-Processor interrupt
1 Enable Master Mode. 0: CPU assisted, 1: Bus Master
4 Interrupt Status. Interrupt pending if set. Write 0 to clear
5 Terminate Co-Processor operation if set
6 Enable Turbo Co-Processor data path. If set removes extra datapath
delay (1 clock).
M+12h (R/W): Pixel Map Select
M+14h D(R/W): Pixel Map n Base
M+18h W(R/W): Pixel Map n Width
M+1Ah W(R/W): Pixel Map n Height
M+1Ch (R/W): Pixel Map n Format
bit 0-2 Bits per pixel. 0: 1bpp, 3: 8bpp, 4: 16bpp, 5: 32bpp
3 Set for Motorola format, clear for Intel format
7 Set if the map is in system memory, clear if in video memory
M+20h W(R/W): Bresenham Error Term
M+24h W(R/W): Bresenham K1
M+28h W(R/W): Bresenham K2
M+2Ch D(R/W): Direction Steps
M+48h (R/W): ROP
M+4Ah (R/W): Destination Color Compare Condition
bit 0-2 Condition.
0: Always true (disable update)
2: Dest == color
4: Dest != color
6: Always false (enable update)
M+4Ch D(R/W): Destination Color Compare Value
M+50h D(R/W): Pixel Bit Mask
M+58h D(R/W): Foreground Color
M+5Ch D(R/W): Background Color
M+60h W(R/W): Operation Dimension 1
M+62h W(R/W): Operation Dimension 2
M+6Ch W(R/W): Mask Map Origin X Offset
M+6Eh W(R/W): Mask Map Origin Y Offset
M+70h W(R/W): Source X Pointer
M+72h W(R/W): Source Y Pointer
M+74h W(R/W): Pattern X Pointer
M+76h W(R/W): Pattern Y Pointer
M+78h W(R/W): Destination X Pointer
M+7Ah W(R/W): Destination Y Pointer
M+7Ch D(R/W): Pixel Operations Register
bit 0-2 Direction
4-5 Drawing Mode
6-7 Mask Pixel Map
12-15 Pattern Pixel Map
16-19 Destination Pixel Map
20-23 Source Pixel Map
24-27 Co-Processor Function Control
28-29 Foreground Source
30-31 Background Source
Note: the co-processor is clearly modeled on the IBM XGA.
ID Oak VGA:
if testinx2($3DE,$D,$38) then
begin
{ We have an OAK }
if testreg2($3DE,$23,$1F) then
if (rdinx($3DE,0) and 2)=0 then _OAK_087
else _OAK_083
else
case inp($3DE) div 32 of
0:_OAK_037C
2:_OAK_067
5:_OAK_077
7:_OAK_057
end;
end;
Modes:
(OTI 067/077/087)
4Eh T 80 60 16 (8x8) Not all 067's
4Fh T 132 60 16 (8x8)
50h T 132 25 16 (8x14)
51h T 132 43 16 (8x8)
52h G 800 600 16 PL4
53h G 640 480 256 P8
54h G 800 600 256 P8
55h G 1024 768 4 PL1/2?
56h G 1024 768 16 PL4
57h G 768 1024 4 ??
58h G 1280 1024 16 PL4
59h G 1024 768 256 P8 OTI-077/87 only
5Ah G 640 480 64k P16 OTI-077 w/Sierra
5Bh G 640 400 32k P15 OTI-077 w/Sierra
5Ch G 640 480 32k P15 OTI-077 w/Sierra
5Dh G 800 600 32k P15
5Eh G 1280 1024 256 P8
5Fh G 640 480 16m P24
60h G 800 600 64k P16
61h G 640 400 256 P8
Note that the OAK-087 BIOS version 1.01B does not set the DAC mode of the
HiColor modes correctly.
(OTI037C "UNIQUE" VGA)
50h T 132 25 16 (8x14)
51h T 132 43 16 (8x8)
52h G 800 600 16 PL4
(OTI037C with NEL Electronics BIOS)
50h G 640 480 16 PL4
51h T 80 30 (16x9)
52h G 1024 480 16 PL4
53h T 80 25 (16x8)
54h T 132 43 (8x8)
55h T 132 25 (14x8)
56h T 132 43 (8x9)
57h T 132 25 (14x9)
58h T 80 43 (8x8)
59h T 80 43 (8x9)
5Ah T 80 60 (8x8)
5Bh G 800 600 16 PL4
5Ch T 100 37 (16x8)
5Dh T 100 75 (8x8)
5Eh G 800 600 16 PL4
6Ah G 800 600 16 PL4
6Bh T 100 37 (16x8)
----------10FF-----------------------------------
INT 10 - VIDEO - OAK VGA BIOS v1.02+ - SET EMULATION
AH = FFh
AL = Emulation
43h CGA emulation
45h EGA emulation
4Dh Hercules emulation
56h VGA emulation
ES:DI -> signature string "Calamity"
Switches to the desired emulation
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -