cga.txt

比较详尽的VGA端口寄存器的文档

IBM Color Graphics Adapter (CGA)

The original CGA was built with discrete logic around an MC6845 display
 controller.

On the original CGA and some clones accessing the video memory during the
active display time caused the display controller to miss some pixels (seen as
"snow"), which is the reason many programs only accesses video memory during
vertical or horizontal retrace. This is fixed in some clones and in EGA/VGA
adapters.

Basic features:
   80x25 text modes in 16colors
   320x200 4color graphics modes
   640x200 2 color graphics mode
   TTL video interface (Red, Green, Blue and Intensity)
   16KB Video RAM and 2KB ROM for 8x8 font.


Clones:
Commodore AGA:
  Combines CGA, MDA, Hercules and Plantronics support in one chip.
Chips & Tech 82c425:
  Supports both CRT and LCD displays. Greyscale on LCD, supports two softfonts
  (up to 8x16 pixels) allowing 512 characters on screen. No Snow.
Chips & Tech 82c426:
  Same as 82c425, but also supports Sleep mode, AT&T 400 line Graphics Mode,
  Color LCDs and upto 32KB video memory.


3D4h (W): Index register.
          The value written to this register selects which of the data
          registers will be accessed at 3D5h.

3D4h index 00h (W): Horizontal Total Register
Bit 0-7  Number of characters (-1) in a scan line incl. retrace.
Note: this register is Read/Write on the CT82c425/6.

3D4h index 01h (W): Horizontal Displayed Register
Bit 0-7  Number of characters (-1) displayed during a scan line.
Note: this register is Read/Write on the CT82c425/6.

3D4h index 02h (W): Horizontal Sync Position Register
Bit 0-7  Number of characters displayed before Horizontal Sync pulse starts.
Note: this register is Read/Write on the CT82c425/6.

3D4h index 03h (W): Horizontal Sync Width Register
Bit 0-7  Number of character clocks during a Horizontal Sync pulse.
Note: this register is ignored on the CT82c425/6.

3D4h index 04h (W): Vertical Total Register
Bit 0-6  Number of character rows in a frame. This is adjusted by the number
         of scanlines in a character (index 9) and the Vertical Adjust (index
         5).
Note: this register is Read/Write on the CT82c425/6.

3D4h index 05h (W): Vertical Total Adjust Register
Bit 0-3  Number of scanlines added to the Vertical Total time.
Note: this register is Read/Write on the CT82c425/6.

3D4h index 06h (W): Vertical Displayed Register
Bit 0-6  Number of character rows displayed per frame.
Note: this register is Read/Write on the CT82c425/6.

3D4h index 07h (W): Vertical SyncPosition Register
Bit 0-6  Number of character rows displayed before the Vertical Sync pulse
         starts.
Note: this register is Read/Write on the CT82c425/6.

3D4h index 08h (W): Interlace Mode Register
Note: this register is ignored on the CT82c425/6 and F8680.

3D4h index 09h (W): Maximum Scan Line Register
Bit 0-3  Number of scanlines (-1) in a character row.
Note: this register is Read/Write on the CT82c425/6.

3D4h index 0Ah (W): Cursor Start Register
Bit 0-4  The scanline (starting from 0) within the character where the
         cursor starts.
    5-6  Cursor Attributes:
           0,2: Cursor is blinking at the blink rate.
             1: Cursor is turned off.
             3: Cursor is blinking at half the blink rate.
         The default blink rate is 1/16 of the frame rate (8 frames on, 8
         off).
Note: this register is Read/Write on the CT82c425/6.

3D4h index 0Bh (W): Cursor End Register
Bit 0-4  The scanline (starting from 0) within the character where the
         cursor ends. If the start position (index 0Ah) is larger than this
         value, no cursor is shown.
Note: this register is Read/Write on the CT82c425/6.

3D4h index 0Ch (W): Start Address High Register
Bit 0-5  The upper 6 bits of the address of the start of the display.
         The lower 8 bits are in index 0Dh.
Note: this register is Read/Write on the CT82c425/6.

3D4h index 0Dh (W): Start Address Low Register
Bit 0-7  The lower 8 bits of the address of the start of the display.
         The upper 6 bits are in index 0Ch.
Note: this register is Read/Write on the CT82c425/6.

3D4h index 0Eh (W): Cursor Location High Register
Bit 0-5  The upper 6 bits of the address of the start of the cursor.
         The lower 8 bits are in index 0Fh.
Note: this register is Read/Write on the CT82c425/6.

3D4h index 0Fh (W): Cursor Location Low Register
Bit 0-7  The lower 8 bits of the address of the start of the cursor.
         The upper 6 bits are in index 0Eh.
Note: this register is Read/Write on the CT82c425/6.

3D4h index 10h (W): Light Pen High Register
Bit 0-5  The upper 6 bits of the latched address of the lightpen strobe.
         The lower 8 bits are in index 11h.
Note: this register is Read/Write on the CT82c425/6.

3D4h index 11h (W): Light Pen Low Register
Bit 0-7  The lower 8 bits of the latched address of the lightpen strobe.
         The upper 6 bits are in index 10h.
Note: this register is Read/Write on the CT82c425/6.

3D4h index D3h (R/W): Grey-level Control Register #1           (CT82c426 only)
bit 0-7  GC10-17. Parameter for the Monochrome Alternate GrayScale algorithm.
         Recommended value is 43h. Bit 3 should be 0.

3D4h index D4h (R/W): Grey-level Control Register #2           (CT82c426 only)
bit 0-7  GC20-27. Parameter for the Monochrome Alternate GrayScale algorithm.
         Recommended value is E6h. Bits 3 and 7 should be 0.

3D4h index D5h (R/W): General-Purpose Register                 (CT82c426 only)
bit   0  General Purpose I/O bit 1. Data to/from the GPIO1 pin.
      1  General Purpose I/O 1 Three State Control.
         If set the GPIO1 pin is three-stated and can be used as an input.
         If clear the pin is an output.
      2  General Purpose I/O 1 Mux Control.
         If set the GPIO1 pin is fed with the data in bit 0, if clear with the
         Display Enable bit (3DAh bit 0).
      4  General Purpose I/O bit 2. Data to/from the GPIO2 pin.
      5  General Purpose I/O 2 Three State Control.
         If set the GPIO2 pin is three-stated and can be used as an input.
         If clear the pin is an output.
      6  General Purpose I/O 2 Mux Control.
         If set the GPIO2 pin is fed with the data in bit 4, if clear with the
         ROMCS/ signal

3D4h index D6h (R/W): Sleep Register                           (CT82c426 only)
bit   0  Sleep Mode Software Enable. If a 1 is written to this bit, the 82c426
         enters sleep mode when the current display fetch completes.
         In sleep mode video memory can not be accessed and the SLEEP pin is
         driven high. If a 0 is written normal operation resumes.
      1  (R) Sleep Mode Output. Reflects the state of the SLEEP output pin.
         1 if the 82c426 is in sleep mode or if the Video Enable bit is 0.

3D4h index D7h (R/W): Panel Size Register                      (CT82c426 only)
bit 0-7  Size of the upper panel (if a two panel system) in scanlines (-1).

3D4h index D8h (R/W): Panel Configuration Register             (CT82c426 only)
bit 0-2  LCD Mode. Panel type:
           0: Single Panel, Single Drive
           1: Dual-Panel, Single Drive