ramdac.txt

比较详尽的VGA端口寄存器的文档

    8-12  N1. Frequency divider. Stored as 1-31, actual value 3-33
   13-15  N2. Divides the frequency. 0: /1, 1: /2, 2: /4, 3: /8
Note: Defines the frequency generate when clock 2 is selected
Note: Frequency is (M/N1)/(1 << N2) *base frequency.M and N1 are the actual
      values, not the stored ones. Typically the base frequency is 14.318 MHz.

REG05 index 03h W(R/W):  f3 PLL M & N1/M2 divider
bit  0-6  M.  Quotient. Stored as 1-127, actual value 3-129
    8-12  N1. Frequency divider. Stored as 1-31, actual value 3-33
   13-15  N2. Divides the frequency. 0: /1, 1: /2, 2: /4, 3: /8
Note: Defines the frequency generate when clock 3 is selected
Note: See index 02h for details

REG05 index 0Ah W(R/W):  Memory Clock
bit  0-6  M.  Quotient. Stored as 1-127, actual value 3-129
    8-12  N1. Frequency divider. Stored as 1-31, actual value 3-33
   13-15  N2. Divides the frequency. 0: /1, 1: /2, 2: /4, 3: /8
Note: Defines the frequency generate for the memory clock
Note: See index 02h for details

REG05 index 0Eh W(R/W):  PLL Control


REG06 (R/W):  Enhanced Command Register
bit 4-7  Mode: 0: Palette (1 pixel/VCLK), 1: Palette (2 pixels/VCLK), 2: 15bit
          (2 VCLKs/pixel), 3: 15bit (1 VCLK/pixel), 4: 24bit (3 VCLKs/pixel)
          - GenDAC only?, 5: 16bit (1 VCLK/pixel), 6: 16bit (2 VCLKs/pixel),
          7: 32bit (2 VCLKs/pixel), 0Eh: 24bit (3 VCLKs/pixel)

REG07 (R/W):  PLL Read Register
bit  0-7  Controls the indexed register read from REG05. Each indexed
          register holds two bytes at the same index. Autoincremented after
          every two reads of REG05.





SGS-Thompson STG1700/2/3 Truecolor DACs:
All the STG DACs have 16bit pixel data path, but the 1700 can not use the
packed 24bit mode where 2 pixels are transferred in 3 pixel clocks.
The 1703 has built-in clock generator.

REG04 (R/W):  Index Low
bit  0-7  Index for the register accessible via REG05. The high byte (always
           0) is in REG07.

REG05 (R/W):  Indexed Register
There are a series of indexed registers in the STG DACs. If REG06 bit 4 is set
they are accessed by the two index bytes to REG02 and then reading or writing
the indexed registers at REG02 (index will autoincrement). If REG06 bit 4 is
clear the index is written to REG04 & REG07 and the indexed register are read
or written at REG05.

REG05 index 00h (R):  Company ID
bit 0-7  44h for SGS-Thompson, 97h for ??

REG05 index 01h (R):  Device ID
bit 0-7  00h for STG1700, 02h for STG1702, 03h for STG1703

REG05 index 02h (R/W?):
bit 0-7  A1h ??

REG05 index 03h (R/W?):  Primary Pixel Mode
bit 0-7  Mode (this register only active if REG06 bit 3 set):
          2: 15bit 1VCLK per pixel
          3: 16bit 1VCLK per pixel
          4: 24bit 2VCLKs per pixel (2x 16bit -> 1x 24bit)
          5:  8bit 1/2 VCLKs per pixel (ie. 16bit -> 2x 8bit)
          9: (not 1700) 24bit 3/2 VCLKs per pixel (3x 16bit -> 2x 24bit)

REG05 index 04h (R/W?):  Secondary Pixel Mode
bit 0-7  same as index 3 ??

REG05 index 05h (R/W?):  PLL Control
bit 0-7  02h - for double clocking (16bit) ???

REG05 index 06h (R/W?):
bit 0-7  00h ??

REG05 index 07h (R/W?):
bit 0-7  88h ??

REG05 index 20h W(R/W):
bit  0-7  B. Quotient
    8-12  N1. Frequency divider.
   13-15  Divider (D). 0: /1, 1: /2, 2: /4, 3: /8
The effective clock is: Ref*D*(B+2)/(N1+2). Ref is the reference clock,
typically 14.31818MHz

REG06 (R/W):  Pixel Command Register
bit   0  Power down the DAC if set
      1  Set to get 8bit DACs in 256color mode, clear to get normal 6bit DACs
      2  Controls intensity ??
      3  If set the DAC is controlled by the indexed registers below.
      4  When set puts the dac into indexed mode, now write the index (2
         bytes) to this register, then each access to this register will read
         or write the particular indexed register and increment the index.
         This is the same index as in REG04/REG07.
    5-7  Selects the Hi/True color mode:  0: Standard (16/256color),
           5: 15bit(32K), 6: 16bit(64K), 7: 24bit(16m)
Note: This register can be accessed by reading REG02 4 times, then the next
      read or write of REG02 will access this register. Any access of REG00,
      REG01 or REG03 will terminate the access to this register, The register
      can only be read or written once per unlock sequence (DAC type 4-1w1r).

REG07 (R/W):  Index High
bit  0-?  High byte of the index in REG04. 0 for all current registers.



Sierra SC15021,25/6 Truecolor DACs:
The SC15021 supports 16bit pixel data path.

REG04 (R/W):  Overlay Write Address

REG05 (R/W):  Overlay Data

REG06 (R/W):  Command Register
bit 1-2  EXT mode select ?
      3  Gamma Correction enabled if set?
      4  If set 3C7h is the index port and 3C8h the data port for an extra
         register, also this register is then accessible directly at 3C6h.
  0,5-7  Mode:
           00h  Palette modes
           04h  32bit RGBx (red first) "double clocked" -  pixel data on both
                rising and falling edge of the dotclock
           05h  32bit BGRx (blue first) "double clocked"
           06h  24bit RGB/32bit RGBx (red first)
           07h  24bit BGR/32bit BGRx (blue first)
           08h  15bit (32K colors) "double clocked"
           09h  15bit (32K colors) "EXT" "double clocked"
           0Ah  15bit (32K colors)
           0Bh  15bit (32K colors) "EXT"
           0Ch  16bit (64K colors) "double clocked"
           0Eh  16bit (64K colors)
Note: This register can be accessed by reading REG02 4 times, then the next
      read or write of REG02 will access this register. Any access of REG00,
      REG01 or REG03 or writes to REG02 will terminate the access to this
      register, however reading of REG02 will not (DAC type 4-1wNr).

REG06 index 8 (R/W):  Auxiliary Control
bit    0  DAC and palette register width in palette modes.
          Set for 8bit and clear for 6 bit
       1  PED 75 IRE.
       2  Power Down.

REG06 index 9 (R):  ID1
bit  0-7  53h ('S')

REG06 index 0Ah (R):  ID2
bit  0-7  Version code. 0/36h/3Ah

REG06 index 0Bh (R):  ID3
bit  0-7  B1h for the SC15025/26, ACh for the SC15021

REG06 index 0Ch (R):  ID4
bit  0-7  41h

REG06 index 0Dh (R/W):  Pixel Mask Low
bit  0-7  ANDed with the pixel data, Low byte. Should normally be FFh.

REG06 index 0Eh (R/W):  Pixel Mask Middle
bit  0-7  ANDed with the pixel data, Middle byte. Should normally be FFh.

REG06 index 0Fh (R/W):  Pixel Mask High
bit  0-7  ANDed with the pixel data, High byte. Should normally be FFh.

REG06 index 10h (R/W):  Pixel Repack
bit    0  (15025/6) Set for 4x 8bit -> 1x 24bit, clear for 1x 8bit -> 8bit,
            2x 8bit -> 1x 16bit or 3x 8biot -> 1x 24bit
     0-3  (15021) Packaging: 2: 8bit -> 2x4bit, 4: 16bit -> 2x8bit,
             5: 3x16bit -> 2x24bit (2/3 clock), 6: 2x16bit -> 24bit (1/2
              clock), 8: 16bit -> 16bit (alternate?), 0: all others

REG06 index 11h (R/W):  Cursor                                         (15021)
bit  0-2  Cursor Delay. 0: None, 4: +1, 5: +2, 6: -1, 7: -2
     3-4  Cursor type. 0: disabled, 1: 3 colors, 2: 2 color MS-Windows style,
             3: 2 color X11 style
       7  Cursor Polarity

REG06 index 12h (R/W):  Secondary Control                              (15021)
bit  0-1  Mix control: 1: 8 -> 16 MixA or 8 -> 15 MixB, 2: 8 -> 16 MixB or
           8 -> 15 MixA, 0 for all others.

REG07 (R/W):  Overlay Read Address





Trident TKD8001 24bit DAC (also 9200CXr,9400CXi,9420DGi internal DAC):

REG06 (R/W):  Command Register
      0  (not 9200) Power down DAC if set ?
      1  (not 9400) In mode 0 this bit when set selects 8bit DACs, when clear
          6bit DACs. Should be set in 24bit mode, clear in 15/16 bit modes ?
    5-7  Mode:  0: Palette (16/256), 5: 15bit (32k), 7: 16bit (64k),
          6: 24bit (16m colors) bit 2 should be set in this mode
Note:  This register can also be accessed at REG02 by reading REG02 four
       times. Then the command register can be read or written at REG02.
       This access will be terminated by any access to REG00, REG01 or REG03
       or after a write to the command register (DAC type 4-Nr1w).




Trident 9440AGi internal 24bit DAC:

REG06 (R/W):  Command Register
      2  If set in the 15/16/24 bit modes pixels with the most significant
         bit set appears to be displayed as if in palette mode ?
    4-7  Mode:  1: 15bit (32k), 3: 16bit (64k), 0Dh: 24bit (16m colors)
         All other values appears to default to palette mode
Note:  This register can also be accessed at REG02 by reading REG02 four
       times. Then the command register can be read or written at REG02.
       This access will be terminated by any access to REG00, REG01 or REG03
       or after a write to the command register (DAC type 4-Nr1w).




TI TLC34058, Brooktree Bt458 DACs
These DACs are intended for high bandwidth systems and are not VGA compatible.
They use 4 or 5 separate pixel ports in parallel for higher bandwidth

REG04 (R/W)  Index Register.
bit  0-7  Index for accesses through 3C6h, 3C7h and 3C9h. For 3C7h and 3C9h
          there is also an internal counter for the (Red, Green and Blue)
          cycle. This counter is reset when this register is written.
          Each access to 3C7h or 3C9h will increment first the RGB counter and
          then this register.

REG05 (R/W)  Palette Data
bit  0-7  Palette data port. 3C8h selects the entry in the palette RAM. Each
          read or write of this register increments index, first through the
          Red, Green & Blue and then increments register 3C8h

REG06 (R/W)  Control Data.
bit  0-7  Data port for the Control registers. 3C8h is the index. Unlike 3C7h
          and 3C9h the index in 3C8h is not increased by reads and writes of
          this register

REG06 index 4 (R/W):  Read Mask Register
bit  0-7  The pixel data is ANDed with this byte before being passed to the
          palette RAM. This is similar to 3C6h in standard VGA systems.

REG06 index 5 (R/W):  Blink Mask Register
bit  0-7  In the blink off period the pixel data is ANDed with the inverse of
          this register, Ie. the '0' bits in this register will protect the
          corresponding bits of the pixel data from blinking, while '1' bits
          will force the corresponding pixel data bits low during the blink
          off period.

REG06 index 6 (R/W):  Command Register
bit    0  OL0 Display Enable. If clear the overlay pin 0 (OL0) is forced to 0
       1  OL1 Display Enable. If clear the overlay pin 1 (OL1) is forced to 0
       2  OL0 Blink Enable. If set (and bit 0 set) the overlay pin 0 toggles
          between 0 and the actual value at the blink rate
       3  OL1 Blink Enable. If set (and bit 1 set) the overlay pin 1 toggles
          between 0 and the actual value at the blink rate
     4-5  Blink Rate Select. Selects the blink rate in vertical periods:
            0: 16on/48off, 1: 16on/16off, 2: 32on/32off, 3: 64on/64off
       6  RAM Enable. If the overlay select pins (OL0-1) are 0 this bit
          selects the output. Set for palette RAM data, clear for overlay
          register 0.
       7  Multiplex Select. Set for 5:1 multiplexing, clear for 4:1
          multiplexing - pixel port E is ignored and should be tied low

REG06 index 7 (R/W):  Test Register
bit  0-3  Selects the data to be returned in bit 4-7 when reading this
          register. Selects upper or lower 4 bits of one of the 3 DAC inputs:
              1: return 4MSB of Red         9: return 4LSB of Red
              2: return 4MSB of Green      10: return 4LSB of Green
              4: return 4MSB of Blue       12: return 4LSB of Blue
     4-7  (R) Data selected by bits 0-3

REG07 (R/W)  Overlay Data
bit  0-7  Overlay data port. 3C8h selects the entry in the overlay RAM (0-3).
          Each read or write of this register increments index, first through
          the Red, Green & Blue and then increments register 3C8h




TI TLC34075, ATI68875 True color DACs
This DAC has an 8bit VGA port and a 32bit pixelport (P). The 32bit pixelport
P can be multiplexed for greater bandwidth. 6 or 8 bit DACs can be controlled
via the 8/6 pin (low=6bit, high=8bit).

REG08 (R/W):  General Control Register
bit    0  If set HSYNCOUT is active high, active low if clear
       1  If set VSYNCOUT is active high, active low if clear
       2  Enables split shift register transfer (VRAM) if set
       3  Enables special nibble mode if set
       4  Pedestal Enable Control. Set for a 7.5 IRE pedestal, clear for a 0
          IRE pedestal
       5  Sync Enable Control. If set enables sync on green.
       7  MUXOUT