ramdac.txt

比较详尽的VGA端口寄存器的文档

REG06 index 40h (R/W):  Cursor Color1 Red
bit  0-7  Red component of the Cursor Color1.

REG06 index 41h (R/W):  Cursor Color1 Green
bit  0-7  Green component of the Cursor Color1.

REG06 index 42h (R/W):  Cursor Color1 Blue
bit  0-7  Blue component of the Cursor Color1.

REG06 index 43h (R/W):  Cursor Color2 Red
bit  0-7  Red component of the Cursor Color2.

REG06 index 44h (R/W):  Cursor Color2 Green
bit  0-7  Green component of the Cursor Color2.

REG06 index 45h (R/W):  Cursor Color2 Blue
bit  0-7  Blue component of the Cursor Color2.

REG06 index 46h (R/W):  Cursor Color3 Red
bit  0-7  Red component of the Cursor Color3.

REG06 index 47h (R/W):  Cursor Color3 Green
bit  0-7  Green component of the Cursor Color3.

REG06 index 48h (R/W):  Cursor Color3 Blue
bit  0-7  Blue component of the Cursor Color3.

REG06 index 60h (R/W):  Border Color Red
bit  0-7  Red component of the Border Color.

REG06 index 61h (R/W):  Border Color Green
bit  0-7  Green component of the Border Color.

REG06 index 62h (R/W):  Border Color Blue
bit  0-7  Blue component of the Border Color.

REG06 index 70h (R/W):  Miscellaneous 1
bit    6

REG06 index 71h (R/W):  Miscellaneous 2
bit    0
       2  If set DACs & LUTs are 8bit wide, if clear only 6bits wide

REG06 index 72h (R/W):  Miscellaneous 3
REG06 index 73h (R/W):  Miscellaneous 4                           (Not RGB525)
REG06 index 82h (R/W):  DAC Sense
REG06 index 84h (R/W):  Misc Red
REG06 index 86h (R/W):  Misc Green
REG06 index 88h (R/W):  Misc Blue
REG06 index 8Eh (R/W):  PLL VCO Div In
REG06 index 8Fh (R/W):  PLL Ref Div In
REG06 index 90h (R/W):  VRAM Mask 0
REG06 index 91h (R/W):  VRAM Mask 1
REG06 index 92h (R/W):  VRAM Mask 2
REG06 index 93h (R/W):  VRAM Mask 3

REG06 index 100h-4FFh (R/W):  "Cursor Data"
Note: The cursor map is either a 64x64x2 (1024 bytes) or 32x32x2 (256bytes).
      The map data is stored with upper lines first, left pixels first. Each
      byte holds 4 pixels, with lowest pixel in bits 0-1 and highest on 6-7.
         High bit:  Low bit:    Resulting Screen data:
             0         0
             0         1
             1         0        Screen data
             1         1

REG07 (R/W):  Index Control
bit   0  If set the index at REG04 is autoincremented by each access of REG06




ICS 5301:
REG06 (R/W):  "Hidden DAC register"
bit 0-1  Power down if set ??
    2-4  Always 0
    5-7  Mode. 1,4,5: 15bit, 3,6: 16bit, 2,7: 24bit
Note: This register can be accessed by reading REG02 4 times, then the next
      read or write of REG02 will access this register. Any access of REG00,
      REG01 or REG03 will terminate the access to this register. The register
      can only be read or written once before the DAC is returned to normal
      mode (DAC type 4-1r1w).




IC Works W30c498, W30c516 Truecolor DACs:
REG06 (R/W):  Command Register
bit 0,2  (?) Clockmode for Mode 2 (2 8bit pixels/VCLK). 0: Clock < 22.5
            MHz, 1: Clock < 45 MHz, 2: Clock >= 45 MHz
      1  In palette modes this bit when set selects 8bit DACs, when clear 6bit
         DACs.
    4-7  Mode: 0: 8bit 1VCLK/pixel, 1: 15bit 1VCLK/pixel, 2: 8bit (2 pixels/
          VCLK), 3: 16bit 1VCLK/pixel, 5: 32bit 2VCLKs/pixel, 6: 16bit
          2VCLKs/pixel, 10: 15bit 2VCLKs/pixel
Note:  This register can also be accessed at REG02 by reading REG02 four times
       The fifth read will access of 3C6h will access this register. Only one
       read or write will be allowed (DAC type 4-1r1w3i), the 6th read returns
       84h, the 7th returns 98h and the 8th read returns 4Fh (at least for the
       w30c516).




MUSIC MU9c1880 and Diamond SS24 Truecolor DACs:
REG06 (R/W):  Command Register
bit 0,6  Red  Byte Position Shift. In 24bit mode delays the fetching of the
         first pixel of each scanline by 1 or 2 bytes to synchronize with the
         start of the first pixel.
           0: no delay, 1: delay 1 byte, 2: delay 2 bytes
  1-3,5  Selects the Hi- or Truecolor mode. 8: 15bit (5-5-5) HiColor,
           0Bh: 16bit (5-6-5) HiColor, 7: 24bit Truecolor (Red byte first).
      4  Pixel Mode Switch. In 15bit mode when this bit is set, the most
         significant bit of each 16bit pixel whether that pixel should be
         displayed as HiColor (bit 15=0) or Pseudo Color (bit 15=1).
         If this bit clear all pixels are displayed as HiColor
         This bit should be clear in 16bit mode and set in 24bit mode.
      7  If clear the DAC is in Pseudo Color mode, all other bits in this
         register are ignored, if set it is in a Hi- or Truecolor mode (15,16
         or 24 bits/pixel).
Note:  This register can also be accessed at REG02 by reading REG02 four times,
       The fifth read will return 8Eh (the ID for the MU9c1880/SS24) and then
       the next read or write of 3C6h will access this register. Only one read
       or write will be allowed (DAC type 5i-1r1w).




MUSIC MU9c4870 High Color(?) DAC
MUSIC MU9c4910 True Color DAC.
MUSIC MU9c9910 True Color DAC & Clock Generator.
REG04 (R/W):  PLL Write Index Register                             (9910 only)
bit 0-3  Selects the index register which will be accessed by the next write
         to REG05.

REG05 (R/W):  PLL Data Register                                    (9910 only)
The PLL registers accessed at this register are indexed via REG04 (writes) and
REG07 (reads). All (?) are two byte registers which are accessed via two reads
or writes (low byte first) each of the indexes have an internal flip-flop to
track low/high byte. Each read of REG05 will increment the read index (with
the flip-flop incremented first). Writes increment the write index (REG04)
similarly.

REG05 index 00h - 07h W(R/W):  f0-f7 PLL Parameters
bit  0-6  M. Numerator.
    8-11  N1. Quotient. Prescales REF for the PLL.
   12-13  N2. Clock divider. Divides the output clock by: 0: /1, 1: /2,
            2: /4, 3: /8
Resultant clock is: REF*(M+1)/((N1+1)*(2^N2)), where REF is the reference
clock, typically 14.31818MHz.

REG06 (R/W):  Command Register
bit   0  Powers down the DAC if set
    5-7  Mode. 5: 15bit, 6: 16bit, 7: 24bit
Note: This register can be accessed by reading REG02 3 times, then the fourth
      read will return the device ID and then the next read or write of REG02
      will access this register. Any access of REG00, REG01 or REG03 or writes
      to REG02 will terminate the access to this register, however reading of
      REG02 will not (DAC type 4i-1wNr).
      The MU9c9910 has ID 44h, the MU9c4910 has ID 82h, the MU9c4870 ??

REG07 (R/W):  PLL Read Index Register                              (9910 only)
bit 0-3  Selects the index register which will be accessed by the next read
         to REG05.




MUSIC MU9c9750 Low Power SYNDAC:
REG04 (R/W):  PLL Write Address Register
bit 0-3  Selects the index register which will be accessed by the next write
         to REG05.

REG05 (R/W):  PLL Parameters
The PLL registers accessed at this register are indexed via REG04 (writes) and
REG07 (reads). As all but index 0Eh are two byte registers which are accessed
via two reads or writes (low byte first) each of the indexes have an internal
flip-flop to track low/high byte. Each read of REG05 will increment the read
index (with the flip-flop incremented first). Writes increment the write
index (REG04) similarly.

REG05 index 00h - 07h W(R/W):  CLK0 f0-f7 PLL Parameters
bit  0-6  M. Numerator.
    8-11  N1. Quotient. Prescales REF for the PLL.
   12-13  N2. Clock divider. Divides the output clock by: 0: /1, 1: /2,
            2: /4, 3: /8
   14-15  PLL Mode Select. 0: Normal PLL mode - the output frequency is
          calculated as: f=REF*(M+1)/((N1+1)*(2^N2)), 1: High-resolution
          Low-frequency mode - same as PLL mode, but the output clock is
          divided by 1024, 2: OFF - The output is set HIGH, 3: Low-resolution
          Low-frequency mode - Output clock is: f=REF/((M+1)*(2^N2))
REF is the reference clock, typically 14.31818MHz. For best results the
following constraints should be observed: REF should be in the 5MHz - 32Mhz
range. REF/(N1+1) should be in the 2MHz - 16MHz range (for REF=14.31818MHz
 N1 should be in the range 1-6) and REF*(M+1)/(N1+1) should be in the 40MHz
 to 80MHz range.

REG05 index 08h W(R/W):  CLK0 fL0 PLL Parameters
Defines the CLK0 output when in LCD mode. Same format as index 0-7

REG05 index 09h W(R/W):  CLK0 fD0 PLL Parameters
Defines the CLK0 output when in Dormant mode. Same format as index 0-7

REG05 index 0Ah W(R/W):  CLK1 fA PLL Parameters
Defines the CLK1 output when in CRT mode and bit 4 of the PLL Control Register
 (index 0Eh) is clear. Same format as index 0-7

REG05 index 0Bh W(R/W):  CLK1 fB PLL Parameters
Defines the CLK1 output when in CRT mode and bit 4 of the PLL Control Register
 (index 0Eh) is set. Same format as index 0-7

REG05 index 0Ch W(R/W):  CLK1 fL1 PLL Parameters
Defines the CLK1 output when in LCD mode. Same format as index 0-7

REG05 index 0Dh W(R/W):  CLK1 fD1 PLL Parameters
Defines the CLK1 output when in Dormant mode. Same format as index 0-7

REG05 index 0Eh (R/W):  PLL Control Register
bit  0-2  CLK0 Select. Selects the CLK0 output in CRT mode (f0 - f7).
       4  CLK1 Select. Selects the CLK1 output in CRT mode. 0: fA, 1: fB
       5  CLK0 External Select Enable. If clear the CLK0 definition (f0-f7)
          is selected by the CS0-CS2 inputs, if set it is selected by bits
           0-2 of this register
       6  CLK0 Master Powerdown. If set the CLK0 PLL is powered down and the
          output is set HIGH.
       7  CLK1 Master Powerdown. If set the CLK1 PLL is powered down and the
          output is set HIGH.

REG06 (R/W):  Command Register
bit   0  LCD mode enable. If set the DAC goes into LCD mode where video flow
         through the DACs is stopped and the palette RAM is only accessed
         to service uP read/writes. The clocks CLK0,CLK1 are forced to the
         state defined in fL0/fL1 regardless of the state of the PLL Control
         register. The internal state of registers and palette RAM is
         maintained. See note
      6  Dormant Mode enable. If set the DAC goes into Dormant mode where
         the video flow though the DACs and the uP interface is stopped.
         The clocks CLK0,CLK1 are forced to the state defined in fD0/fD1
         regardless of the state of the PLL Control register. The internal
         state of registers and palette RAM is maintained. See note
Note: The CRT, LCD and Dormant modes are selected by a combination of the
      bits in this register and the PD0,PD1 input pins (x is don't care):
 PD1:  PD0:  Bit 6:  Bit 0:   Mode:  DAC:  RAM Access:   CLK0:    CLK1:
  1     0      0       0       CRT    On    Video&uP     f0-f7    fA,fB
  x     1      0       0       LCD    Off      uP         fL0      fL1
  1     0      0       1       LCD    Off      uP         fL0      fL1
  0     0      x       x     Dormant  Off     None        fD0      fD1
  x     x      1       x     Dormant  Off     None        fD0      fD1
Setting PD1=1 and PD0=0 allows full control from this register

REG07 (R/W):  PLL Read Address Register
bit  0-3  Selects the index register which will be accessed by the next read
          to REG05.




Oak OTI-66HC HiColor DAC:
REG06 (R/W):  "Hidden" Command Register
bit   0  If set the DAC powers down
    5-7  DAC mode. 5: 15bit, 6: 16bit
Note: This register can be accessed by reading REG02 4 times, then the next
      read or write of REG02 will access this register. Any access of REG00,
      REG01 or REG03 or writes to REG02 will terminate the access to this
      register, however reading of REG02 will not (DAC type 4-1wNr).




S3 86c708 (GenDac aka ICS5342) and 86c716 (SDAC aka ICS5300).

REG02 (R):  "Hidden DAC" register                                     (86c716)
Bit  4-7  7 for the 86c716.
Note: This is a special register overlaying the PEL register activated by an
      internal counter. Each access to 3C7h-3C9h resets the counter and each
      access to 3C6h increments it. When the counter reaches 4 this register
      is returned. The fifth read returns another register

REG04 (R/W):  PLL Write Register
bit  0-7  Controls the indexed register written at REG05. Each indexed
          register holds two bytes at the same index. Autoincremented after
          every two writes of REG05.

REG05 index 00h W(R/W):  f0 PLL M & N1/M2 divider
bit  0-6  M.  Quotient. Stored as 1-127, actual value 3-129
    8-12  N1. Frequency divider. Stored as 1-31, actual value 3-33
   13-15  N2. Divides the frequency. 0: /1, 1: /2, 2: /4, 3: /8
Note: Defines the frequency generate when clock 0 is selected
Note: See index 02h for details
      Possibly hardwired to 25.175MHz

REG05 index 01h W(R/W):  f1 PLL M & N1/M2 divider
bit  0-6  M.  Quotient. Stored as 1-127, actual value 3-129
    8-12  N1. Frequency divider. Stored as 1-31, actual value 3-33
   13-15  N2. Divides the frequency. 0: /1, 1: /2, 2: /4, 3: /8
Note: Defines the frequency generate when clock 1 is selected
Note: See index 02h for details
      Possibly hardwired to 28.322MHz

REG05 index 02h W(R/W):  f2 PLL M & N1/M2 divider
bit  0-6  M.  Quotient. Stored as 1-127, actual value 3-129