ramdac.txt

比较详尽的VGA端口寄存器的文档

       times. Then the command register can be read or written at REG02.
       This access will be terminated by any access to REG00, REG01 or REG03
       or after a write to the command register (DAC type 4-Nr1w).

REG07 (R/W):  Cursor Read Address                                        (482)
bit 0-1?  Selects the palette register which will be read at REG05




BrookTree Bt484, Bt485, AT&T 20c504/5 Truecolor DACs:
The 485 and 505 has the extra register at REG0A and supports 64x64 cursor
The 484 & 504 appears to be limited to 110MHz, the 485/505 to 135MHz

REG04 (R/W):  Cursor/Overscan Write Address
bit 0-7  The PEL data register (0..255) to be written to REG05.
Note: After writing the 3 bytes at REG05 this register will increment, pointing
      to the next data register.

REG05 (R/W):  Cursor/Overscan Data
bit 0-5  Color value
Note:  Each read or write of this register will cycle through first the
       registers for Red, Blue and Green, then increment the appropriate
       address register.
Note: the registers REG04,REG05,REG07 works like the normal REG00,REG01,REG03
      registers, except that a separate set of palette registers (16 overlay
      registers ?) are being accessed.
      Index 00h  Overscan color
            01h  Cursor Color 1 (Background)
            02h  Cursor Color 2 (Foreground)
            03h  Cursor Color 3
Note: if the DAC is in 6bit mode (REG06 bit 1 is 0) the 2 upper bits of the
      cursor colors are ignored.

REG06 (R/W):  Command Reg 0
bit   0  Power Down. If set the DACs and RAM power is turned off, but the RAM
         still retains data, if clear the RAMDAC is operating normally
      1  Set if DAC and palette registers are 8bit DACs, clear if 6bit.
      2  Sync on Red if set
      3  Sync on Green if set
      4  Sync on Blue if set
      5  Set for 7.5 IRE pedestal, clear for 0.0 IRE.
      6  Disables internal clocking if set
      7  (485,505) Enable CR3. If clear the Status register is present at
          REG0A, if set 3C8h determines which register is present at REG0A:
            00h    Status Register
            01h    Command Register 3

REG07 (R/W):  Cursor/Overscan Read Address
bit 0-7  The PEL data register (0..255) to be read from REG05.
Note: After reading the 3 bytes at REG05 this register will increment,
      pointing to the next data register.

REG08 (R/W):  Command Reg 1
bit    0  In 15/16bit 1:1 mode selects the pixel port (A-B or C-D) to take
          pixel data from. Clear for A-B, set for C-D. See bit 1.
       1  PORTSEL. In 15bit 1:1 mode (bit 2 set & bit 3 clear), this bit if
          set causes pin P7D (most significant bit of the C-D port) to select
          whether the 15bit pixel data is taken from port A-B or port C-D,
          thus allowing real-time switching between video sources.
       2  SPARSE. Set if 16bit data is 1:1, clear if it is muxed 2:1
       3  Set in 5/6/5 mode, clear in all other modes
       4  If set decodes True-color pixel data (5/5/5, 5/6/5 or 8/8/8 mode),
          directly, if clear each component (R-G-B) of the pixel data is used
          is used as a separate index to the palette RAM for the specific RGB
          component, allowing non-linear scales (gamma correction) for each
          color-component. REG09 bit 2 controls the indexing.
     5-6  Bits per pixel. 0: 24, 1: 15/16, 2: 8, 3: 4

REG09 (R/W):  Command Reg 2
bit  0-1  Cursor mode. 0: Disabled, 1: 3-Color, 2: Windows, 3: X11 Style
       2  Sparse or Contigous Indexing. In Look-up True-color modes (REG08 bit
          4 clear) selects whether each color component is shifted right or
          left before being used as an index to the palette. If set the pixel
          data is treated as the least significant bits of the index
          (Contigous index), if clear as the most significanty bits (Sparse
          index).
       3  Set in interlaced modes (used for the cursor).
       4  Selects input clock. 0: PCLK0, 1: PCLK1
       5  If clear the dac takes data from the VGA port and each byte is a one
          byte palette index regardless of the state in Command Register 1, if
          set pixel data is taken from pixel ports A-D and data format is
          controlled by Command Register 1
       6  Test Path enabled if set.
       7  SCLK (Video shift clock) disabled if set.

REG0A (R):  Status Reg
bit 4-7  Product ID ?
           4: AT&T20c504, 0Dh: AT&T20c505, 8-Bh: Bt484/5
Note: The two registers at REG0A are selected by bit 7 of REG06.

REG0A (R/W):  Command Reg 3                                   (485,505 only)
Bit  0-1  Bits 8-9 of the Palette Write Address (3C8h)
       2  Set if using 64x64 cursor, clear if 32x32 cursor.
       3  If set the Clock Doubler is enabled and the input clock is doubled.
Note: The two registers at REG0A are selected by bit 7 of REG06.
      This register does not exist on the Bt484

REG0B (R/W):  Cursor Ram Data
bit  0-7  Data port for the Hardware Cursor Map.
          There are either 2 128byte (32x32bit) or 2 512 byte (64x64bit) maps
          depending on REG0A bit 2. The first is the cursor image and the
          second is the cursor shape.
          To update the cursor map, write the start address to REG00and start
          writing to this register. The index will increment for each byte.

REG0C W(R/W):  Hardware Cursor X-position
bit 0-11  The X-position of the rightmost pixel of the hardware cursor

REG0E  W(R/W):  Hardware Cursor Y-position
bit 0-11  The Y-position of the lower scanline of the hardware cursor




Chrontel CH8391 and CH8398:
REG04 (R/W):  Clock RAM Write Address
bit  0-?  Selects the register that is writable at REG05. The first write
          accesses the low byte of the register and the second the high byte.
Note: Reading this register 4 times will cause the next access of this
      register to go to the "Hidden Clock" register.

REG04 (R/W):  Clock Select Register
bit  0-3  Selects the Video Clock.
     4-6  Selects the Memory Clock
       7  Frequency hold. If set the video and memory clock selects in bits
           0-6 are ORed with the actual inputs from the clock select pins
Note: This register is accessed6 by reading REG04 4 timers first.

REG05 (R/W):  Clock RAM Data Register
Note: each indexed register addressed here is 16bit wide and thus must be
      read/written as two bytes, low byte first.

REG05 index 00h-0Fh W(R/W):  Video Clock Select 0-15
bit  0-7  N. Numerator. Effective value (n) is N+8. The following N values
           may give unstable output: 0-7, 10-15, 19-23, 28-31, 37-39, 46-47
           and 55.
    8-13  M. Denominator. Effective value (m) is M+2. It is recommended to
           use N<11 for best clock performance
   14-15  K. Clock Divider. Effective divider (k) is: 0: 1, 1: 2, 2: 4, 3: 8
The resulting clock is: ref*n/(m*k) where ref is the reference clock, usually
 14.31818MHz and n,m and k are the effective (as opposed to coded) factors
Note: The CH8398 apparently has Video Clock 0 hardcoded as 25.175MHz and
      Video Clock 1 hardcoded as 28.322. The CH8391 does not.

REG05 index 10h-17h W(R/W):  Memory Clock Select 0-7
Probably same coding as the Video Clocks.

REG06 (R/W):  Control Register (CH8391)
bit    0  Power Down if set
       1  If set the DAC and palette registers are 8bit wide (256 colors of
           16Mcolors), if clear 6bit (256 colors of 256K colors)
     5-7  Color mode. 0: Palette, 5: 15bit, 6: 16bit, 7: 24bit
Note: This register can also be accessed by reading 3C6h 4 times in a row.
      The 4th read will return the chip ID (B3h for the CH8391) and the 5th
      read or write will access this register ("1r/w" type Cmd register).

REG06 (R/W):  Control Register (CH8398)
bit    0  Power Down if set
       2  Always set ??
     4-7  Color mode. 0: Palette, 1: 15bit, 3: 16bit, 5: 24bit, 6: 16bit,
           7: 24bit, 11: 24bit, 12: 15bit
Note: This register can also be accessed by reading 3C6h 4 times in a row.
      The 4th read will return the chip ID (C0h for the CH8398) and the 5th
      read or write will access this register ("1r/w" type Cmd register).

REG07 (R/W):  Clock RAM Read Address
bit  0-?  Selects the register that is readable at REG05. The first read
          accesses the low byte of the register and the second the high byte.




Cirrus Logic 542x/3x internal DAC.
 - How close is this to the Cirrus Logic CL-GD5200 & Acumos ADAC1 ?
REG02 (R/W):  Hidden DAC Register
bit  0-3  Extended Mode Select. If bit 6 and 7 are both set this field
          selects the DAC mode:
              0:  5-5-5 15bit Sierra HiColor
              1:  5-6-5 16bit "XGA" HiColor
              5:  (5422+) 8-8-8 24bit TrueColor. This mode also exists on the
                    5420 rev1, but is not documented.
            6/7:  (5428+) DAC Power-down
              8:  (5428+) 8bit Greyscale.
              9:  (5428+) 3-3-2 8bit RGB
       4  32K Color Control. If set bit 15 (MSB) of a 15bit pixel selects
          whether the pixel is HiColor(bit 15 = 0) or palette data(bit 15 = 1,
          bit 0-7 is the palette index). This bit only has effect in 5-5-5
          15bit modes.
       5  Clocking Mode. If set Clocking Mode 2 will be selected and data will
          only be latched on the rising edge of DCLK, if clear Clocking Mode 1
          will be selected and data will be latched on both the rising edge
          (low byte) and falling edge (high byte) of DCLK. This bit only has
          effect in 15/16 bit modes as all other modes will use Clocking Mode
          2. Clocking Mode 1 should only be used for externally supplied DCLK
          and pixel data.
       6  Enable ALL Extended Modes. If bit 7 is set and this bit is clear the
          DAC is in 5-5-5 15bit Sierra HiColor mode, if both bit 7 and this
          bit are set bits 0-3 determines the DAC mode.
       7  Enable 5-5-5 Mode. If set the DAC is in an advanced mode, depending
          on the other bits in this register, if clear the DAC is in VGA
          compatible palette mode.
Note: This register is accessed by reading REG02 four times to unlock this
      register, then the next read or write of REG02 will access this register.
      After reading or writing this register the register is locked and this
      register can only be accessed be redoing the 4 reads of REG02 etc. Any
      access to REG00,REG01,REG03 will also lock this register. The 5428 is the
      exception where reads of this register will NOT lock it.
Note: When REG02 is 0FFh the access to this register described above does
x      not always work.
Note: This register does not exist on the 5401/5402 and the 5420 rev A.




IBM RGB514, RGB524, RGB525, RGB528 Truecolor DAC w/PLL:
REG04 W(R/W):  Index
bit  0-?  Selects the indexed register that will be accessed by the next read
          or write of REG06. If REG07 bit 0 is set this index is
          autoincremented by each access of REG06.

REG06 index 00h (R):  Rev
bit  0-7  Revision. F0h for the RGB524, ? for the RGB514, RGB525,RGB528

REG06 index 01h (R):  Id
bit  0-7  Chip ID. 2 for the RGB524, ? for the RGB514,RGB525,RGB528

REG06 index 02h (R/W):  Misc Clock
bit    0  Set for internal (PLL) clock ??
       1  Set for double clock

REG06 index 03h (R/W):  Sync
REG06 index 04h (R/W):  Hsync Pos
bit  0-3  Hsync Position ?

REG06 index 05h (R/W):  Power Management
REG06 index 06h (R/W):  DAC Options
bit    1  Fast slew if set ?
       3  Sync on Green if set

REG06 index 07h (R/W):  Palette Control
REG06 index 08h (R/W):  System Clock                             (Not RGB525?)
REG06 index 0Ah (R/W):  Pixel Format
bit  0-2  Pixel format. 3: 8bpp, 4: 15/16bpp, 6: 32bpp

REG06 index 0Bh (R/W):  8bpp
REG06 index 0Ch (R/W):  16bpp
bit    1  Set for 16bpp (5:6:5), clear for 15bpp (5:5:5)

REG06 index 0Dh (R/W):  24bpp
REG06 index 0Eh (R/W):  32bpp
REG06 index 10h (R/W):  PLL Control 1
bit    0  Set to use 8 internal clocks with separate numerators, clear to
          use 16 internal clocks with a common numerator (index 14h).
     1-2  Set to 1 ??

REG06 index 11h (R/W):  PLL Control 2
bit  0-3  Selects the PLL clock used (0-7 if index 10h bit 0 set, 0-15 if it
          is clear).

REG06 index 14h (R/W):  PLL Ref Div Fix
bit  0-4  N. Numerator. Guess 0 not valid. Used for f0-f15 if index 10h bit 0
          is clear.

REG06 index 15h W(R/W):  Sysclk Ref/VCO Div                       (Not RGB525)
bit  0-4  N. Numerator. Guess 0 not valid

REG06 index 16h (R/W):  Sysclk VCO Div                            (Not RGB525)
bit  0-5  M. Multiplier. 65-128, Stored as 0-63.
     6-7  DF. Divider. 0: /8, 1: /4, 2: /2, 1: /1. (Div=1,2,4,8).
Note: Memory Clock. The effective clock is: Ref*(M+65)/(N*Div), where Ref is
      the reference clock, typ 14.31828MHz and N the numerator from index 15h

REG06 index 20h-2Fh (R/W):  PLL Clock 0-15 (f0-f15)
bit  0-5  M. Multiplier. 65-128, Stored as 0-63.
     6-7  DF. Divider. 0: /8, 1: /4, 2: /2, 1: /1. (Div=1,2,4,8).
Note: Only active if index 10h bit 0 is clear. The effective clock is:
      Ref*(M+65)/(N*Div), where Ref is the reference clock, typ 14.31828MHz
      and N is the Numerator from index 14h.

REG06 index 20h-2Eh W(R/W):  PLL Clock 0-7 (m0/n0..)
bit  0-5  M. Multiplier. 65-128, Stored as 0-63.
     6-7  DF. Divider. 0: /8, 1: /4, 2: /2, 1: /1. (Div=1,2,4,8).
    8-12  N. Numerator. Guess 0 not valid
Note: Only active if index 10h bit 0 is set. The effective clock is:
      Ref*(M+65)/(N*Div), where Ref is the reference clock, typ 14.31828MHz

REG06 index 30h (R/W):  "Cursor Control"
bit  0-1  Cursor type. 0: Disabled, 2: Windows?, 3: X11 cursor
       2  Set for 64x64 cursor, clear for 32x32 cursor
       3
       5  Set for ??

REG06 index 31h W(R/W):  "Cursor X position"
bit  0-?  The horizontal position of the hardware cursor

REG06 index 33h W(R/W):  "Cursor Y position"
bit  0-?  The vertical position of the hardware cursor

REG06 index 35h (R/W):  Cursor Hot-Spot X

REG06 index 36h (R/W):  Cursor Hot-Spot Y