ramdac.txt

比较详尽的VGA端口寄存器的文档

REG02 index 3 (R):  ID Register
bit  0-7  76h for the ADV7160, 79h for the ADV7162

REG02 index 4 (R/W):  Pixel Mask Register
bit  0-7  The pixel inputs (R, G and B) are anded with this value. Set to FFh
          for normal operation.

REG02 index 5 (R/W):  Command Register 1
bit    0  Calibration Control. If set the LOADIN/LOADOUT synchronization
          circuit is calibrated on every vertical sync (REG03 bit 5 must be 0)
       1  Test Mode Control. Enable test mode if set
       2  Should be set to 0
       3  Hi-Byte Control. If set the high byte of the Address Register
          (REG00) is accessible, if clear it is not (ADV7150 compatible).
     4-5  PS Function Control. Controls how the PS0/1 inputs are used.
           0: Palette Select Mode. The PS0/1 inputs selects between 4 devices
          by comparing with REG03 bits 6-7 on a pixel by pixel base,
           1: (ADV7160) Bypass Mode. PS1 switches between Palette Mode and
          Bypass Mode on a pixel by pixel basis. Bits 6-7 controls the Bypass
          Mode. Bypass mode should not be selected in Command Register 2
          (REG02 index 6) and by this field at the same time, 2: Overlay Mode.
          PS0/1 select one of the three overlay colors (PS0/1 = 0 for pixel
          data), 3: Ignore PS Inputs. The PS0/1 inputs are completely ignored.
     6-7  Bypass Color Mode Control. Controls the bypass mode switching.
           0: 15bit bypass, 1: 16bit bypass, 2: 24bit bypass

REG02 index 6 (R/W):  Command Register 2
bit  0-1  Should be set to 0
       2  /SYNC Recognition on Green. If set the /SYNC input is encoded on the
          IOG output.
       3  Pedestal Enable Control. Set for a 7.5 IRE blanking pedestal, clear
          for a 0 IRE pedestal.
     4-7  True-Color/Bypass/Pseudo-Color Mode Control. 0: 8bit Pseudo Color
          on R0-7, 4: 8bit Pseudo Color on G0-7, 8: 8bit Pseudo Color on B0-7,
           9: 16bit Bypass Mode on G0-7 + R0-7, 10: 15bit Bypass Mode on G0-7
           + R0-6, 11: 16bit True Color Mode on G0-7 + R0-7, 12: 15bit True
          Color Mode on B3-7 + G3-7 + R3-7, 13: 15bit True Color Mode on G0-7
           + R0-6, 14: 24bit True Color Mode, 15: 16bit Bypass Mode

REG02 index 7 (R/W):  Command Register 3
bit  0-1  PROGCKOUT Frequency Control. Determines the PROGCKOUT output clock
          frequency relative to the pixel clock (CLOCK). 0: CLOCK/4,
           1: CLOCK/8, 2: CLOCK/16, 3: CLOCK/32
     2-4  /BLANK Pipeline Delay Control. Controls the delay of the /BLANK
          signal (in addition to the overall device pipeline delay Tpd).
          Adds N * LOADOUT to the /BLANK delay.
       5  Should be set to 0
     6-7  Pixel Multiplex Control. 0: 1:1 MUXING - LOADOUT = CLOCK, 1: 2:1
          MUXING - LOADOUT = CLOCK/2, 2: 8:1 MUXING - LOADOUT = CLOCK/8
          (Pseudo Color Mode only), 3: 4:1 MUXING - LOADOUT = CLOCK/4,

REG02 index 8 (R/W):  Command Register 4
bit    0  HDTV Sync Control. If set the /TRISYNC input is encoded enabling a
          Tri-Level Sync output.
       1  /SYNC Recognition Control on Red. If set the /SYNC input is encoded
          on the IOR output.
       2  /SYNC Recognition Control on Blue. If set the /SYNC input is encoded
          on the IOB output.
     3-4  Gain Control. Selects the Video Standard used.
          Value: DAC Gain: Video Standard            Black to White current:
            0      3996    RS343A, Sync & Pedestal       660mV  17.62mA
            1      4224    RS343A, Sync, No Pedestal     699mV  18.63mA
            2      4311    RS343A, No Sync, No Pedestal  714mV  19.05mA
            3      5592    RS170,  Sync & Pedestal       925mV  24.67mA
       5  Signature Clock Control. Enables the Signature Analyser if set
       6  Signature Reset. To reset the Signature Analyser write 0, then 1
          to this field.
       7  Signature Acquire. Enables Signature Acquisition if set

REG02 index 9 (R/W):  PLL Command Register
bit    0  PLL Control. Enables the PLL if set
       1  RSEL Bit Control. When set the PLL Reference Divider is in units of
           2, if clear in units of 1. See REG02 index 0Ch for details.
       2  VSEL Bit Control. When set the PLL Feedback Divider is in units of
           2, if clear in units of 1. See REG02 index 0Fh for details.
       3  Should be set to 0
     4-5  Output Divide Control. Selects the Post divider for the VCO
           0: VCO/1, 1: VCO/2, 2: VCO/4, 3: VCO/8
     6-7  PLL S Control. The lower two bits of the PLL Feedback value.
          See REG02 index 0Fh for details.

REG02 index 0Ah (R):  Status Register
bit    0  Set if either of the IOR,IOG or IOB outputs exceeds the internal
          voltage of the /SENSE comparator circuit

REG02 index 0Bh (R):  Revision Register
bit  0-?  Silicon Revision Code.

REG02 index 0Ch (R/W):  PLL R Register
bit  0-6  Controls the PLL Reference Divider value together with the RSEL bit
          (index 9 bit 1). If this field is set to 0 the PLL stops.
          The effective value is: (1+RSEL)*(This_Field+2).
          This allows all values from 3-129 and all even values from 130-258.

REG02 index 0Dh (R/W):  Command Register 5
bit  0-5  Should be set to 0
       6  Set to enable the internal PLL, clear to disable it
       7  Should be set to 0

REG02 index 0Fh (R/W):  PLL V Register
bit  0-6  Controls the PLL Feedback Divider value together with the VSEL bit
          (index 9 bit 2). If this field is set to 0 the PLL stops.
          The effective value is: (1+VSEL)*(4*(This_Field+2)+ S)
          where S is the value from REG02 index 0Ch bits 6-7.
          This allows all values from 12-519 and all even values from 520-1038

REG02 index 10h (R):  Signature Red Register
REG02 index 11h (R):  Signature Blue Register
REG02 index 12h (R):  Signature Green Register
REG02 index 13h (R):  Signature Misc Register

REG02 index 200h W(R/W):  Cursor X Register
bit 0-15  The X coordinate of the cursor as a 2's complement (-4096 to 4095).
Note: Low byte in index 200h, High byte in index 201h
Note: When accessing the cursor X/Y registers (index 200h to 203h) the index
      register autoincrements with each access. These registers must be
      updated in the order 200h,201h,202h and then 203h

REG02 index 202h W(R/W):  Cursor Y Register
bit 0-15  The Y coordinate of the cursor as a 2's complement (-4096 to 4095).
Note: Low byte in index 202h, High byte in index 203h
Note: When accessing the cursor X/Y registers (index 200h to 203h) the index
      register autoincrements with each access. These registers must be
      updated in the order 200h,201h,202h and then 203h

REG02 index 204h (R/W):  Cursor Control Register
bit  0-1  Cursor Mode Control. 1: X11 cursor, 2: XGA cursor
          Pattern:    X11 cursor:        XGA cursor:
             0        Transparent        Color 1
             1        Transparent        Color 2
             2        Color 1            Transparent
             3        Color 2            Bit-Wise Complement (XOR cursor)
       2  Cursor Enable. Enables the cursor if set
       3  Interlace Control. Set for interlaced modes.
     4-7  Should be set to 0

REG02 index 303h (R/W):  Color 2


REG02 index 304h (R/W):  Color 1

REG02 index 400h-7FFh (R/W):  Cursor Image
bit  0-7  The 64x64 cursor image is stored in these 1024 bytes with 4 2bit
          "pixels" per index. Index 400h holds the 4 leftmost pixels of the
          first (topmost) line, index 40Fh the 4 rightmost and index 7FFh the
          4 rightmost pixels of the last line.

REG02 index 0-2, 0Eh, 14h and 15h are labeled as "Test Registers"

REG03 (R/W):  Mode Register
bit    0  Reset Control. To reset the pixel port sampling sequence to start
          with port A, write 1, then 0 and finally 1 to this bit.
       1  RAM-DAC Resolution Control. If set the LUT and DACs are 10bits, if
          clear LUT and DACs are 8bits (lower 2 inputs to the 10bit DACs are
          forced to 0).
       2  MPU Data Bus Width. If set the MPU interface is 10 bits wide
     3-4  Operational Mode Control. 0 for normal operation
       5  Calibrate LOADIN. To calibrate the LOADIN/LOADOUT synchronization
          circuit write 0, then 1 to this bit. Should be 0 for normal
          operation.
     6-7  Palette Select Match Bits Control. If Command Register 1 (REG02
          index 5) bits 4-5 is 0 the PS0-1 bits are compared with these two
          bits on a pixel per pixel base allowing realtime switching between
          up to 4 devices




ATI 68860/68880 Truecolor DACs:
REG08 (R/W):
bit 0-?  Always 2 ??

REG0A (R/W):
bit 0-?  Always 1Dh ??

REG0B (R/W):  (GMR ?)
bit 0-7  Mode. 82h: 4bpp, 83h: 8bpp, A0h: 15bpp, A1h: 16bpp, C0h: 24bpp,
          E3h: 32bpp  (80h for VGA modes ?)

REG0C (R/W):  Device Setup Register A
bit   0  Controls 6/8bit DAC. 0: 8bit DAC/LUT, 1: 6bit DAC/LUT
    2-3  Depends on Video memory (= VRAM width ?) . 1: Less than 1Mb, 2: 1Mb,
           3: > 1Mb
    5-6  Always set ?
      7  If set can remove "snow" in some cases (A860_Delay_L ?) ??




AT&T 20c49x,Winbond W82c490 Truecolor DACs:

REG06 (R/W):  Command Register
bit   0  (W82c490, some ATTs) Power Down Enable. If set the DACs and video
          multiplexers are powered down. The CPU interface is still working.
      1  (490,491) In mode 0 this bit when set selects 8bit DACs, when clear
            6bit DACs.
    2-4  Exists, but appears to have no function ?
    5-7  Mode:  0-3: Palette, 4: 15bit (32k) the two bytes are latched on
         opposite edges of the dotclock (similar to SC11486), 5: 15bit (32k),
           6: 16bit (64k), 7: 24bit (16m)
Note: This register can also be accessed by reading REG02 4 times, then the
      next read or write of REG02 will access this register. Any access of
      REG00, REG01 or REG03 will terminate the access to this register. The
      register can only be read or written once before the DAC is returned to
      normal mode (DAC type 4-1r1w).




AT&T 20c498,21c498,22c498 Truecolor DACs (Also IC Works?):
REG06 (R/W):  Command Register
bit 0,2  (22c498) Clockmode for Mode 2 (2 8bit pixels/VCLK). 0: Clock < 22.5
            MHz, 1: Clock < 45 MHz, 2: Clock >= 45 MHz
      1  In palette modes this bit when set selects 8bit DACs, when clear 6bit
         DACs.
    4-7  Mode: 0: 8bit 1VCLK/pixel, 1: 15bit 1VCLK/pixel, 2: 8bit (2 pixels/
          VCLK), 3: 16bit 1VCLK/pixel, 5: 24/32bit 2VCLKs/pixel, 6: 16bit
          2VCLKs/pixel
Note:  This register can also be accessed at REG02 by reading REG02 four times,
       The fifth read will access of 3C6h will access this register. Only one
       read or write will be allowed (DAC type 4-1r1w2i), the 6th read returns
       84h and the 7th returns 98h (don't know about the 20c498).




Avance Logic ALG1201 Truecolor DAC:
REG06 (R/W):  "Hidden Command register"
bit 5-7  Mode. 5: 15bit, 6: 16bit, 7: 24bit
Note: This register can also be accessed by reading REG02 4 times, then the
      next read or write of REG02 will access this register. Any access of
      REG00, REG01 or REG03 will terminate the access to this register. The
      register can only be read or written once before the DAC is returned to
      normal mode (DAC type 4-1r1w).




BrookTree Bt477:
REG06 (R/W):
bit   0  DAC powerdown. If set the DAC powers down
      1  DAC Width. If set the DAC and palette registers are 8bit wide, if
          clear only 6bit wide (as std VGA).
      5  IRE control ?? seems to affect the output intensity ?




BrookTree Bt481/482:

REG00 index 0 (R/W):  Ind Pixel Mask

REG00 index 1 (R/W):  Overlay Mask

REG00 index 2 (R/W):  Command Register B
bit    0  Set to power down the DAC (Sleep mode).
       1  DAC Width. If set the DAC and palette registers are 8bit wide, if
          clear only 6bit wide (as std VGA).
       2  Sync on Red if set
       3  Sync on Green if set
       4  Sync on Blue if set
       5  Set for 7.5 IRE, clear for 0.0 IRE pedestal (affects DAC range).
       6  Enables the Overlay registers if set

REG00 index 3 (R/W):  Cursor Register                                    (482)
bit  0-1  Cursor type. 0: disabled, 1: 3-color, 2: Windows, 3: X11 style
       2  Cursor Op disabled if set?
       3  If clear reads/writes to REG04,REG05,REG07 will access the cursor
          palette, if set the cursor pattern data will be accessed instead.
       4  Set in interlaced modes
       5  Selects External cursor if set

REG00 index 4 W(R/W):  Cursor X                                          (482)
bit 0-11  Cursor X position

REG00 index 6 W(R/W):  Cursor Y                                          (482)
bit 0-11  Cursor Y position
Note: the indexed DAC registers are accessed by setting bit 0 of REG06. Then
      REG00 is the index register and REG02 is the data register.

REG04 (R/W):  Cursor Write Address                                       (482)
bit 0-1?  Selects the palette register which will be written at REG05
            0: Overscan, 1: Cursor Background, 2: Cursor Foreground

REG05 (R/W):  Cursor RAM Data                                            (482)
bit  0-7  Cursor palette data
Note: If REG00 index 3 bit 3 is clear this works like the palette address&data
      registers at REG00,REG01&REG03 except that a separate palette is
      accessed. Each read/write of this register will increment first through
      the red,green,blue sequence and then the Address register (REG04/REG07).
      If REG00 index 3 bit 3 is set REG04/REG07 are the lower 8 bits of the
      index into the 1024 byte palette pattern RAM, which will increment for
      each access to this register.

REG06 (R/W):  Command Register A
bit    0  If set the Bt481/2 indexed DAC registers can be accessed by setting
          REG00 to the index and reading or writing the data at REG02.
     4-7  Mode. 0: Palette, 8: 15bit (Dual edge), 9: 24bit (Dual edge),
            Ah: 15bit (32K), Ch: 16bit (Dual edge), Eh: 16bit (64K),
            Fh: 24bit (16m). The Dual edge modes transfers data on both the
          rising and falling edges of the pixel clock.
Note:  This register can also be accessed at REG02 by reading REG02 four