ramdac.txt

比较详尽的VGA端口寄存器的文档

RAMDACs

AcuMos:
ADAC1        15/16/24 bit.

Analog Devices:
ADV471       6bit DAC       15 overlay registers
ADV475       6bit DAC       15 overlay registers
ADV476       6bit DAC
ADV477       8bit DAC       15 overlay registers
ADV478       6/8bit DAC     15 overlay registers

ADV7129      True-Color 192bit pixel bus
ADV7160      True color 96bit pixel bus. 10bit DACs. HW cursor. PLL
ADV7162

ATI:
ATI68830     15/16/24bit    Up to 80 MHz    !
ATI68860     15/16/24bit    "Spectra" DAC for Mach64
ATI68875     15/16/24bit    Up to 135 MHz   ! Used in ATI Graphics Ultra +
                             and Pro.  Similar to TI34075
ATI68880                    Very similar to 68860

AT&T:
ATT20c40x   ??
ATT20c490    15/16/24 bit.  6/8 bit DAC.
ATT20c491    15/16/24 bit.  6/8 bit DAC w/gamma correction
ATT20c492    15/16/18 bit   6bit DACs. w/gamma correction
ATT20c493    15/16/18 bit   6bit DACs
ATT20c497    24bit          ?
ATT20c498    24bit          16bit pixel databus  !
ATT21c498    24bit          16bit pixel databus  ! What's the diff?
ATT22c498    24bit          16bit pixel databus  !


Avance Logic:
ALG1101      16-bit.        Appears to be different from the other HiColor
                            DACs.
ALG1201      24bit
ALG1301      24bit

Avasem:
AV3676       6bit DAC

Brooktree:
Bt458        8bit DAC       upto 135MHz. Not VGA compatible
Bt476        6bit DAC.
Bt477        6/8bit DAC
Bt478        6/8bit DAC.
Bt481        15/16bit
Bt482        15/16bit
Bt484        15/16/24bit    6/8bit DAC. Has hardware cursor.
Bt485        15/16/24bit    6/8bit DAC. Has hardware cursor.

Chrontel
CH8391
CH8398       15/16/24bit and Clock chip

Cirrus Logic
CL-GD5200    15/16/24 bit   Same as Acumos ADAC1

Diamond:
SS2410       15/24 bit.     OEM version of MUSIC MU9c1880

IBM:
RGB514       24bit.  144pin. HW cursor, 64bit pixel bus. Clock generator.
                             packed 24bit pixels
RGB524       24bit.  144pin. HW cursor, 64bit pixel bus. Dual clock generator
                             packed 24bit pixels
RGB525       24bit.  208pin. HW cursor, 64bit pixel bus. Clock generator
                             packed 24bit pixels
RGB526       24bit.  144pin. HW cursor, 64bit pixel bus. Dual clock generator
                             packed 24bit pixels
RGB528       24bit.  208pin. HW cursor, 128bit pixel bus. Dual clock generator
                             supports 24bit packed pixels
RGB530       24bit.  208pin. HW cursor. 96bit pixel bus. Clock generator,
                             10bit DACs and LUTs, window attribute table
RGB561       24bit.  304pin. HW cursor. 200bit pixel bus. Clock generator.
                             10bit DACs and LUTs
RGB624       24bit.  144pin. HW cursor, 64bit pixel bus, Dual clock generator
                             packed 24bit pixels, YUV to RGB conversion


ICS:
ICS5300      24bit          Combined RAMDAC & Clock chip
ICS5301
ICS5342      24bit          Combined RAMDAC & Clock chip

IC Works:
W30c498                     Similar to AT&T 20c498
W30c516      44pin          "ZoomDAC"

Inmos:
IMSG171
IMSG173
IMSG174
IMSG176      6bit DAC
IMSG178

MUSIC:
MU9C1710     6 bit DAC
MU9C4870     15/16 bit      Similar to Sierra "Mark 3".
MU9C1880     15/16/24bit    Same as SS24
MU9C4910     15/16/24bit
MU9C9910     15/16/24bit    As 4910, but with dual clock generator onchip
MU9C9750     6bit DAC       with onchip clock generator w/powerdown
MU9C9760     6bit DAC       with onchip clock generator
MU9C4160     15/16/24bit    16bit wide pixelbus
MU9C9160     15/16/24bit    As 4160, but with onchip clock generator

OAK:
OTI66        6bit DAC
OTI66HC      15/16bit       Similar to Sierra "Mark 3"

S3:
86c716 (SDAC)       Combined RAMDAC & Clockchip. Same as ICS 5300
86c708 (GenDAC)     Combined RAMDAC & Clockchip. Same as ICS 5342

Samsung:
KDA476       6bit DAC       Standard '476


SGS-Thompson:
STG1700      24bit          16bit pixel path.
STG1702      24bit  44pin   As 1700 + Supports "2 24bit pixels/3 VCLKs"
STG1703      24bit  68pin   As 1702 + onchip Clock Generator

Sierra Semiconductors:
Sierra  "Mark1":       Only works if the VGA controller can send a byte on
                       both the rising AND falling edge of the dot clock.
SC11481      15-bit.        6-bit DAC.   Overlay.
SC11486      15-bit.        6-bit DAC.
SC11488      15 bit.        6/8 bit DAC. Overlay.

Sierra  "Mark2":
SC11482      15-bit.        6-bit DAC.   Overlay.
SC11483      15-bit.        6-bit DAC.
SC11484      15-bit.        6/8 bit DAC. Overlay.

Sierra  "Mark3":
SC11485      15/16 bit.     6-bit DAC.   Overlay.
SC11487      15/16 bit.     6-bit DAC.
SC11489      15/16 bit.     6/8 bit DAC. Overlay.

SC15020      24bit          16bit pixel path
SC15021      24bit          16bit pixel path
SC15025      24 bit.
SC15026      24 bit.


TI:
TLC34058     8bit           upto 135MHz. Not VGA compatible
TLC34075     24bit          upto 135MHz
TVP3010      24bit          As 302x, but 32bit pixel path
TVP3020      24bit          64bit pixel path
TVP3025      24bit          As 3020 + Programmable Clock

Trident:
TKD8001      24bit

UMC:
UM70c171     Standard 6bit DAC
UM70c178     15/16 bit      Similar to Sierra "Mark 3"
UM70c188     24bit

Winbond:
W82c476      6bit DAC       Standard '476
W82c478      6/8bit DAC     Standard '478
W82c490      15/16/24bit    Very close to the AT&T20c492


15-bit modes have 5 bits of each basic color:
bit  0- 4 blue.
     5- 9 green.
    10-14 red.
The pixel is stored in two bytes in Intel style (little endian).

16-bit modes have 5 bits of red and blue, and 6 bits of green:
bits 0- 4  blue.
     5-10  green.
    11-15  red.
The pixel is stored in two bytes in Intel style (little endian).

24-bit modes have 8 bits of each basic color:
bits 0- 7  blue.
     8-15  green
    16=23  red.
The pixel is stored in three bytes in Intel style (little endian).



The DACs are addressed on port 3C6h-3C9h. Advanced DACs have 1 or 2 extra
address lines (RS2 and RS3). These may be controlled from high address bits
(A10-A15) (Compaq or Weitek cards) or from registers (S3, ATI....).
In the following the DAC registers are named REGxx as follows:

            I/O:     RS2:     RS3:
REG00       3C8h      0        0
REG01       3C9h      0        0
REG02       3C6h      0        0
REG03       3C7h      0        0
REG04       3C8h      1        0
REG05       3C9h      1        0
REG06       3C6h      1        0
REG07       3C7h      1        0
REG08       3C8h      0        1
REG09       3C9h      0        1
REG0A       3C6h      0        1
REG0B       3C7h      0        1
REG0C       3C8h      1        1
REG0D       3C9h      1        1
REG0E       3C6h      1        1
REG0F       3C7h      1        1



Many of these DACs can access REG06 using only the 4 standard DAC addresses
(3C6h-3C9h) by reading 3C6h 4 or 5 times, then REG06 can be accessed at 3C6h.

  Type:

  "1r/w"   Read 3C6h 4 times, then the next read or write of 3C6h will access
           the command register.


Forcing HiColor DACs into command mode:
Note: This works on the Sierra, ATT, Winbond DACs and clones, not on the
 Brooktree or TI DACs, also the MUSIC DACs will require an extra read of 3C6h.

procedure dactocomm;   {switches DAC to command register}
var x:word;
begin
  x:=inp($3C8);    {clear old state}
  x:=inp($3C6);
  x:=inp($3C6);
  x:=inp($3C6);    {Read $3C6 4 times.}
  x:=inp($3C6);
end;

Now reads and writes to $3C6 will access the command register. Depending on
the DAC type you may have multiple read/writes, one write/multiple reads or
one read/write of the command register before it switches back to the PEL
register. Any access to $3C7-$3C9 will switch back to the PEL mask register.


Forcing HiColor DACs into normal mode:

procedure dactopel;  {switches DAC back to normal mode}
var x:word;
begin
  x:=inp($3C8);
end;




HiColor DACs:     (Sierra SC1148x, MUSIC MU9C4870, OAK OTI66HC, UMC UM70C178)

REG04 (R/W):  Overlay RAM Write Address               (SC11481/2/4/5/8/9 only)
bit 0-3  Write index for the Overlay registers.

REG05 (R/W):  Overlay RAM                             (SC11481/2/4/5/8/9 only)
bit 0-5  Data port for the overlay registers. Works like the PEL data register
         (3C9h) except that the overlay registers are accessed and the Overlay
         Address registers are used for indexes.
Note: on the SC11484/8/9 the Color Look-up Table and the overlay registers are
      24bits wide (rather than 18bits) if the 8/6 pin is high.

REG06 (R/W):  Command Register
bit   0  (SC11487) (R) Set if bits 5-7 is 1 or 3, clear otherwise
    3-4  (SC11487) Accesses bits 3-4 of the PEL Mask registers (REG02)
      5  (not SC11481/6/8)
         If set two pixel clocks are used to latch the two bytes
         needed for each pixel. Low byte is latched first.
         If clear the low byte is latched on the rising edge of the
         pixel clock and the high byte is latched on the falling edge.
         Only some VGA chips (ET4000 and C&T655x0) can handle this.
      6  (SC11485/7/9, OTI66HC, UM70C178) Set in 16bit (64k) modes (Only valid
           if bit 7 set). On the SC11482/3/4 this bit is read/writable, but
           has no function. On the SC11481/6/8 this bit does not exist.
      7  Set in HiColor (32k/64k) modes, clear in palette modes.
Note:  This register can also be accessed at 3C6h by reading 3C6h four times,
       then all accesses to 3C6h will go the this register until one of the
       registers 3C7h, 3C8h or 3C9h is accessed.

REG07 (R/W):  Overlay RAM Read Address              (SC11481/2/4/5/8/9 only)
bit 0-3  Read index for the Overlay registers.



Analog Devices ADV7160,ADV7162 True-Color Video RAM-DAC:
The ADV716x DACs are not really VGA compatible, but with proper initialisation
palette writing and the PEL register can be simulated.
REG00 W(R/W):  Address Register
bit 0-10  Controls the index read or written at REG01 or REG02.
          Regardless of the bus width this register is accessed by two 8bit
          reads or writes at this address, low byte first.

REG01


REG02 Control Registers