cirrus.txt

比较详尽的VGA端口寄存器的文档

Note: See index 1Bh for the frequency calculation

3C4h index 1Fh (R/W):  BIOS Write Enable and MCLK select
bit  0-5  MCLK frequency bit 0-5

3CEh index  0  (R/W):  Set/Reset
bit  0-3  Write Mode 5 background color bits 0-3
     4-7  Write Mode 5 background color bits 4-7
Note: See the VGA section for the use of this register in write mode 0-3

3CEh index  1  (R/W):  Enable Set/Reset
bit  0-3  Write Mode 4/5 foreground color bits 0-3
     4-7  Enable SR plane 0-3 or Write Mode 4/5 foreground color bits 0-3
Note: See the VGA section for the use of this register in write mode 0-3

3CEh index  5  (R/W):  Mode
bit  0-1  Write mode:  See the VGA section for modes 0-3.
       2  Write mode bit 2 if 3CEh index 0Bh bit 2 is set
           mode 4:  Foreground write ?
           mode 5:  Fore and background write
       3  Enable Read Color Compare
       4  Enable odd/even (3C4h index 4 bit 2).
       5  Shift 2 bits per byte
       6  256 Color Mode

3CEh index 09h (R/W):  Offset Register 0
bit  0-6  4k Primary/Low bank number
          If 3CEh index 0Bh bit 0 is set references to A000h-A7FFh use this
          bank register. If clear references to A000h-AFFFh use this bank
          register.

3CEh index 0Ah (R/W):  Offset Register 1
bit  0-6  4k High bank number
          If 3CEh index 0Bh bit 0 is set references to A800h-AFFFh use this
          bank register.

3CEh index 0Bh (R/W):  Extension Control
bit    0  If set references to A000h-A7FFh use 3CEh index 9 as bank register,
          and references to A800h-AFFFh use 3CEh index 0Ah as bank register.
          If clear all references to A000h-AFFFh use 3CEh index 9 as bank
          register.
       1  Enable BY8 Addressing for 256 color modes
       2  Enable Extended Write Modes if set (mode 4 and 5)

3d4h index 00h (R/W):  Horizontal Total (CX00)
bit  0-7  Horizontal Total (-5)
Note: This register is used in 80 column and mode 13h (3C4h index 1 bit 3
      clear or 3CEh index 5 bit 6 set)

3d4h index 01h (R/W):  Horizontal Total (CX01)
bit  0-7  Horizontal Total (-5)
Note: This register is used in 50 column modes (3D4h index 1 bit 3 set or 3CEh
      index 5 bit 6 clear)

3d4h index 02h (R/W):  LFS Signal Vertical Counter Value Compare (CX02)
bit  0-7  Used if autocentering is not selected.
Note: This register selected for 3C2h bits 2-3 = 3 ??

3d4h index 03h (R/W):  LFS Signal Vertical Counter Value Compare (CX03)
bit  0-7  Used if autocentering is not selected.
Note: This register selected for 3C2h bits 2-3 = 2 ??

3d4h index 04h (R/W):  LFS Signal Vertical Counter Value Compare (CX04)
bit  0-7  Used if autocentering is not selected.
Note: This register selected for 3C2h bits 2-3 = 1 ??

3d4h index 05h (R/W):  LFS Signal Vertical Counter Value Compare (CX05)
bit  0-7  Used if autocentering is not selected.
Note: This register selected for 3C2h bits 2-3 = 0 ??

3d4h index 06h (R/W):  LFS Overflow (CX06)
bit  0-1  Bits 8-9 of the LFS compare for 3C2h bits 2-3 = 3
     2-3  Bits 8-9 of the LFS compare for 3C2h bits 2-3 = 2
     4-5  Bits 8-9 of the LFS compare for 3C2h bits 2-3 = 1
     6-7  Bits 8-9 of the LFS compare for 3C2h bits 2-3 = 0

3d4h index 06h (R/W):  Vertical Total (RX06)
bit  0-7  Vertical Total (-2)

3d4h index 07h (R/W):  Color TFT Panel Control Signal (CX07)
bit    0  If set FPVDCLK is always active, if clear FPVDCLK is gated by
          display enable
       1  FPVDCLK is inverted if set
       2  If set use LLCLK as HSYNC
       3  If set use LFS as VSYNC

3d4h index 07h (R/W):  Vertical Overflow (RX07)
bit    0  Vertical Total bit 8
       1  Vertical Displayed bit 8
       2  Vertical Sync Start bit 8
       3  Vertical Blank Start bit 8
       4  Line Compare bit 8
       5  Vertical Total bit 9
       6  Vertical Displayed bit 9
       7  Vertical Sync Start bit 9

3d4h index 08h (R/W):  STN Color Panel Data Format (CX08)
bit    0  If set 8bit data, if clear 16bit
       1  Set for Dual shift clk STN, clear for single
       2  Set for testing purposes only
       3  Set to Shorten LP width, clear to Lengthen LP width
       4  Set to enable foreground text enhancement
       5  Set for Single Scan Mono Panels, clear for Dual Scan
       6  Set for testing purposes only
       7  Set to boost contrast for Mono Panels

3d4h index 09h (R/W):  TFT Panel Data Format (CX09)
bit  0-1  Data format. 0: 9bit(333), 2: 12bit(444), 1,3: 18bit direct
     2-4  Shiftclock delay from internal character clock to TFT hsync(LLCLK)
          signal

3d4h index 0Ah (R/W):  TFT Panel HSYNC Position Control (CX0A)
bit  0-7  Horizontal counter to generate TFT panel VSYNC signal.
          Set in multiples of 8 VCLKs (80 column character clocks)

3d4h index 0Bh (R/W):  Panel Adjustment Control (CX0B)             (6235 only)
bit  0-4  Number of LLCLKs between upper and lower panel halfs
     5-6  Offset adjustment for gray-scale shading

3d4h index 10h (R/W):  Vertical Sync Start (RX10)
bit  0-7  VSYNC Start

3d4h index 11h (R/W):  Vertical Sync End (RX11)
bit  0-3  VSYNC End.
       4  Clear Vertical Sync Interrupt
       5  Enable Vertical Sync Interrupt
       6  Select 5 refresh cycles
       7  Write protect index 0-7.

3d4h index 15h (R/W):  Vertical Blank Start (RX15)
bit  0-7  Vertical Blank Start

3d4h index 16h (R/W):  Vertical Blank End
bit  0-7  Vertical Blank End

3d4h index 19h (R/W):  Interlace End
bit  0-7  Ending Horizontal Character Count for Odd field VSYNC.
          Typically half the horizontal total

3d4h index 1Ah (R/W):  Miscellaneous Control
bit    0  Enable Interlace sync/video data in Graphics mode or interlace only
          in Text mode. Set if an interlaced mode.
       1  Enable Double-Buffered Display Start Address

3d4h index 1Bh (R/W):  Extended Display Control
bit    0  Display Start Address bit 16. Bit 0-15 are in 3d4h index Ch-Dh.
       1  Enable Extended Address Wrap. Set to enable access to video memory
          beyond 128K (16bit memory) or 256K (32bit memory)
       5  Set RAMDAC blanking=display enable signal (no border)
       6  Select Text mode Fast-Page (132 color text)
       7  Disable Cursor blink in Text Mode

3d4h index 1Ch (R/W):  Flat-Panel Interface
bit    0  Invert LFS signal
       1  Invert LLCLK signal
       2  Enable MCLK power-down during suspend mode
       3  Protect CRTC for LCD timing:
            3d4h index 0,1,6,7(bits 0,2,5,7), 10h and 11h
       5  Enable extra LLCLK. Used for adjusting 242 line dual panel
     6-7  Flat-Panel type. 0: Dual Mono, 1: Plasma/EL, 2: STN color,
           3: TFT color

3d4h index 1Dh (R/W):  Flat Panel Display Control
bit    0  Enable Auto Center
       1  Enable Auto Expand:  3C2h bit 6-7: 1: 400/200 lines, 2: 350, 3: 480.
       2  Enable VGA access to reset Backlight Timer
       3  Enable input ACTi to reset Backlight Timer
       4  Suspend mode Clock source. If set use OSC, if clear use pin 32KHz.
       5  Enable VGA access to reset Standby Timer
       6  Enable input ACTi to reset Standby Timer
       7  Enable access to LCD timing register at CRTC alternate index if set

3d4h index 1Eh (R/W):  Flat Panel Shading
bit    0  Enable Planar Graphics Mode Dithering
       1  Enable Text mode Contrast Enhancement
     2-3  # of shades for Flat Pane:
          Mono:   0: 16, 1: 64, 2: 128, 3:256
          Color:  0: 4K, 1-3: 256K
       4  Reverse Video Graphics Modes
       5  Reverse Video Text Modes
     6-7  Shade Mapping.
           0: 18bit LUT output to 64 shades with NTSC weighting
           1: green LUT output (6 bit to 64 shades).
           2: Display data before Attribute Controller to 64 shades
           3: Attribute Controller output, 6bitrs to 64 shades

3d4h index 1Fh (R/W):  Flat Panel MOD control
bit  0-6  If bit 7 is set LLCLK = (this value) + 180h
          if clear this is the number of scan lines after which the MOD pin
          will change polarity.
       7  Modulation select. Set for internal Modulation, clear for external

3d4h index 20h (R/W):  Power Management
bit    0  Text Mode Shading Control. If set the text shades are derived the
          same way as the graphics, if clear the text shades are derived
          directly from the FG/BG data.
     1-2  Select Refresh Rate. 0: 8ms, 2: 64ms, 2: self refresh, 3: no refresh
       3  Activate Suspend Mode (timer override)
       4  Activate Standby Mode (timer override)
       5  Enable LCD mode if set
       6  Enable CRT mode if set
       7  set pin STANDBY to 'activate' output

3d4h index 21h (R/W):  Power Down Timer Control
bit  0-3  Standby Mode Timer Control. 0: disable timer, 1-15: minutes
     4-7  Backlight Timer Control (FPBack)

3d4h index 23h (R/W):  Suspend Mode Input Switch Debounce Timer
bit    0  FPVcc output state (if bit1 set)
       1  FPVcc control override
       2  FPBack output state (if bit3 set)
       3  FPBack control override
     4-7  Time for input SUSPEND to remain active before entering suspend
          mode. 0: disable timer checking, 1-15: seconds

3d4h index 25h (R/W):  Part Status Register
bit  0-7  Part Status. Used for factory testing only.

3d4h index 27h (R):  Part ID register
bit  0-1  Revision Level
       3  Set to 1 ???
     6-7  Device Identifier.
            0: CL-GD6205    (C9h  rev -BL)
            1: CL-GD6235    (89h  rev -BK)
            2: CL-GD6215    (48h)
            3: CL-GD6225    (09h  rev -BK)

3d4h index 29h (R/W):  Configuration Read Back
bit    0  Bus Type Select. 0: Local Bus, 1: ISA bus
     1-2  Local Bus Type
       3  DRAM Type Select. 0: Dual CAS DRAM, 1: Dual write enable DRAM
       4  Active NPD (no power down) input
       5  Power up/down cycling activity



GD5402, 542x and 543x series:
Also CL-GD754x Nordic/Viking LCD controllers

94h (W):  102 Access Control Register
bit    5  POS 102 Access. If clear register 102h is accessible, if set 102h is
          not accessible.
Note: This register only accessible if the chip is configured for 3C3h sleep
      (CF[3]=0) and for ISA or local bus.

102h (R/W):  POS102 Register
bit    7  Video Subsystem Enable. If set (and bit 4 of 3C3h or 46E8h is also
          set) the chip is enabled, if clear the chip is disabled and only
          responds to accesses to this register (5420 and 5422), the 5424-29
          also responds to accesses to 3C3h.
Note: For MicroChannel systems this register is only accessible when the
      -CD_SETUP pin is low, for other systems it is accessible if bit 4 of
      3C3h/46E8h is set.

3C3h (R/W):  MicroChannel Sleep Address Register                     (5424-29)
bit    7  Video Subsystem Enable. If set the chip is enable, if clear the chip
          is disabled and only responds to accesses to this register
Note: This register only available in MicroChannel systems.

3C3h (R/W):  Motherboard Sleep Address Register                      (5424-29)
bit    3  Video Subsystem Enable. If set the chip is enabled, if clear the
          chip is disabled and only responds to this register, 102h and the
          BIOS, all other registers and the video memory will not respond.
       4  Setup. If set the chip is in setup mode and only this register and
          102h can be accessed, other registers and display memory does not
          respond, if this bit clear the chip is in normal mode.
Note: This is the same registers as 46E8h. The register is mapped at 3C3h,
      46E8h or disabled depending on bus and chiptype. The 5420 and 5422
      always maps it at 46E8h. The 5424-29 maps it at 3C3h (Motherboard
      systems CF[3]=0) or 46E8h (CF[3]=1) depending on bit 3 of the
      Configuration Register, which is sampled at power-on from MD[16-31].
      MicroChannel systems disables this register

3C4h index  2  (R/W):  Map Mask
bit  0-7  Enable writing pixel bits 0-7 in Extended Write mode 4 and 5, and in
          write mode 1 if BY8 addressing is enabled (3CEh index 0Bh bit 1
          set), otherwise use only bits 0-3 as normal VGA.
Note: See the VGA section for the normal use of this register

3C4h index  4  (R/W):  Memory Mode Register
bit    0  Reserved, indicates text/graphics mode in standard VGA
Note: See the VGA section for the normal use of this register

3C4h index  6  (R/W):  Unlock ALL Extensions                        (not 5429)
bit  0-2,4  Writing 12h to this register enables extensions.
            Read back 0Fh if locked.
            Bits 3,5-7 are ignored on write.
Note: on the 5429 the extensions are always enabled.

3C4h index  7  (R/W):  Extended Sequencer Mode
bit    0  Enable High-Resolution 256 Color modes if set.
          For the 5429 this disables the Set/Reset logic (3CEh index 0 and 1)
     1-2  (542x,02)  or
     1-3  (543x) Select CRTC Character Clock Divider.
             0: Normal operation
             1: Clock/2 for 16bit pixels. In this mode the video clock is
                programmed for twice the number of pixels (= the number of