cirrus.txt

比较详尽的VGA端口寄存器的文档

       1  Enable FPHDE Control. If set the FPHDE signal will be active during
          horizontal display and vertical retrace time, if clear it is active
          during horizontal and vertical display time.
       2  Flat Panel Drive. If set 100%, if clear 60%
       3  GD6440 Core at 3 Volts. If set 5V, if clear 3.3V

3CEh index E9h (R/W):  Flat Panel Type Control                     (6440 only)
bit  0-2  Flat Panel Size Selection. 0: 640x480, 1: 640x400,
            2: 1280x1024/1280x960
       3  Flat Panel Scan Type. Set for single scan, clear for dual-scan.
     5-6  Extra Line Clock Enable. 0,1: None, 2: 1 extra, 3: 2 extra line
          clocks

3CEh index EAh (R/W):  Flat Panel Power Control                    (6440 only)
bit    0  (R) Power Sequence Status. Indicates if we are in the middle of a
          flat panel power on/off sequence.
       1  (R) Standby on Status
       2  Sequencer Flat Panel Power. Set to sequence the flat panel on, clear
          to sequence the panel off. The sequence takes app. 0.5 seconds.
     3-5  Standby Mode Selection
       6  Enable External Suspend Pin if set

3CEh index EBh (R/W):  Flat Panel Standby Timer                    (6440 only)
bit  0-7  Standby Timer interval in 15 second units.

3CEh index ECh (R/W):  Flat Panel Misc 1 Control                   (6440 only)
bit  0-1  Vertical Alignment Control. 0: Top, 1: Bottom, 2,3:Center
       2  Enable Horizontal Centering if set
       3  Grayscale Offset Value. set for 4, clear for 13
          Set if a CL-GD6340 is present ??
     4-5  Display Type Select. 0: CRT, 1: Flat Panel, 2,3: SimulSCAN
       6  Grayscale Offset Pattern Select. Set for monochrome grayscale offset
          values are used, if clear green grayscale offset values are used.
       7  Invert FPVDE (Flat Panel Vertical Display Enable) if set

3CEh index EDh (R/W):  Flat Panel Retrace FPCLK                    (6440 only)
bit  0-4  Programmed Burst of Line Clocks. The number of line clocks during
          retrace. The frequency is selected by bits 5-6
     5-6  Retrace Line Clock Control
       7  Fast Line Clock. If bit 5-6 are 3 this selects a fast line clock:
          If set use a period of 64 MCLKs with a 16 MCLK pulse, if clear use a
          period of 32 MCLKs with a pulse of 8 MCLKs.

3CEh index EEh (R/W):  Flat Panel Test Control                     (6440 only)
bit  0-7  Reserved
Note: this register is used for testing and should not be used.

3CEh index F0h (R/W):  Flat Panel Clock Control                    (6440 only)
bit  0-3  FPVDCLK Control selects the clock for the display from MCLK
     4-5  FPVDCLK Enable Control
       6  Invert FPVDCLK (Flat Panel Video Clock Signal) if set
       7  Invert FPHDE (Flat Panel Horizontal Display Enable) if set

3CEh index F1h (R/W):  Flat Panel Data Control                     (6440 only)
bit  0-4  Flat Panel Video Data Output Format Control
       5  FPHSYNC/FPVSYNC Polarity Source Control. If set the sync polarity is
          controlled by bits 6-7, if clear by 3C2h bits 6-7.
       6  FPHSYNC Polarity Control. If set inverts the FPHSYNC (Flat Panel
          Horizontal Sync)
       7  FPVSYNC Polarity Control. If set inverts the FPVSYNC (Flat Panel
          Vertical Sync)

3CEh index F2h (R/W):  Flat Panel AC Modulation                    (6440 only)
bit  0-7  The half period of the square wave output to the MOD pin in line
          clocks. Usually does not divide evenly into the panel size.

3CEh index F3h (R/W):  Flat Panel FPHSYNC Skew                     (6440 only)
bit  0-6  FPHSYNC Skew in internal master clocks. Allows adjustment for
          specific panels.

3CEh index F4h (R/W):  Flat Panel FPVSYNC Skew                     (6440 only)
bit  0-4  FPVSYNC Skew. Allows the end of FPVSYNC to be delayed 0..31
       5  FPVSYNC Width. If set FPVSYNC is two line clocks, if clear one.
     6-7  FPHSYNC Width. Adjust the width of FPHSYNC.

3CEh index F5h (R/W):  Memory Clock Select Factor                  (6440 only)
bit  0-4  Memory Clock Numerator "N"
     5-7  Memory Clock Denominator "D"
          The Memory Clock = 14.31818MHz * (N+)/(D+)

3CEh index F6h (R/W):  CRT Clock Select "N" Factor                 (6440 only)
bit  0-6  CRT Clock Numerator "N"
       7  Clock Source Control. If set the CRT clock is determined by the
          "N/D" formula, if clear by 3C2h bits 2-3.
Note: The Video Clock = 14.31818MHz * (N+1)/((D+1) * (divide factor))

3CEh index F7h (R/W):  CRT Clock Select "D" Factor                 (6440 only)
bit  0-3  CRT Clock Denominator "D"
     4-5  CRT Clock Divide
       6  Memory Clock Inverted if set
       7  CRT Clock Inverted if set

3CEh index F8h (R/W):  Flat Panel Mapping RAM Pointer              (6440 only)
bit  0-5  Pointer to the Mapping RAM for I/O Read/Write. Index into Mapping
          RAM. Read and write via index F9h.
       7  Enable I/O Access of Mapping RAM if set

3CEh index F9h (R/W):  Flat Panel Mapping RAM Data                 (6440 only)
bit  0-7  Mapping RAM Data. Reads and writes to this register go to the byte
          in Mapping RAM selected by index F8h.

3CEh index FAh (R/W):  Flat Panel Stippling Control                (6440 only)
bit    0  Enable 32 Shades in All Stippling Cases if set
     1-2  Stippling Select
     3-5  Stippling Bit Select
       6  Enable Inter-modulation if set. Should only be set on TFT color
          panels and if the stippling output is less than 4 bits.

3CEh index FBh (R/W):  Flat Panel Color Control                    (6440 only)
bit    0  Blue Color Weighting. If set the weighting is (BLUE *2)/16.
          Used for sum2gray on monochrome panels.
       1  Green Color Weighting. If set the weighting is (GREEN*9)/16
     2-3  Red Color Weighting
       4  Green Data from LUT. If set only green data is output from the LUTs
          (Look Up Tables). Monochrome STN panels only
       5  Enable Reverse Video in Graphics Modes if set. Panels only
       6  Enable Reverse Video in Text Mode if set. Panels only.

3CEh index FCh (R/W):  Flat Panel Frame Color 1                    (6440 only)
bit  0-3  Frame Color Bits for Red The Red component of the color for the
          non-displayed part of the panel (Border).
       4  Enable Frame Color if set

3CEh index FDh (R/W):  Flat Panel Frame Color 2                    (6440 only)
bit  0-3  Frame Color Bits for Blue. The blue component of the color for the
          non-displayed part of the panel (Border).
     4-7  Frame Color Bits for Green. The Green component of the color for the
          non-displayed part of the panel (Border).


3CEh index FEh (R/W):  Flat Panel Miscellaneous Spare 2          (6440 only ?)
bit  0-7  Reserved

Video Modes:

002Dh  G   640   400   256  P8
002Eh  G   640   480   256  P8
002Fh  G   648   480   256  P8      ;Weird resolution
0030h  G   800   600   256  P8
0037h  G  1024   768    16  PL4
0041h  T   100    50    16  TXT
0042h  T   100    60    16  TXT
0044h  T   100    25    16  TXT
0051h  T   132    50    16  TXT
0052h  T   132    60    16  TXT
0053h  T    80    60    16  TXT
0054h  T   132    25    16  TXT
0064h  G   800   600    16  PL4
006Ah  G   800   600    16  PL4




GD62xx series:
The 62xx series is very similar to the early 54xx.
The 62xx series can display simultaneously on CRT and LCD (SimulSCAN).
The 62xx series always has 512KB. Mixed 3.3V and 5V. Pixel clock up to 65MHz
 (5V) or 40MHz (3.3V).
There are two extra register banks (CX and RX) at 3d4h. How to select ?

3C4h index  2  (R/W):  Map Mask
bit  0-7  Enable writing pixel bits 0-7  ?????
Note: See the VGA section for the normal use of this register

3C4h index  6  (R/W):  Unlock ALL Extensions
bit  0-2,4  Writing 12h to this register enables extensions.
            Read back 0Fh if locked.
            Bits 3,5-7 are ignored on write.

3C4h index  7  (R/W):  Extended Sequencer Mode
bit    0  Enable High-Resolution 256 Color modes if set
     4-6  (R) Configuration switch 0-2 (MD[14:12])

3C4h index  8  (R/W):  Miscellaneous Control
bit  0-2  Switch 1-3 Readback (Panel type, Monitor type, Local bus config).
       3  Select active polarity of input SUSPEND for suspend mode.
         .If set low is true, if clear high is true (default at reset).
       4  Enable IO(60h) read detect to reset backlight timer
       5  Enable IO(60h) read detect to reset standby timer
       6  Disable MSC16* for Display Memory
       7  Select symmetrical DRAM addressing for paged-mode on CRT
          Set when using DRAM 9-bit addressing at 132 col CRT

3C4h index  9  (R/W):  Scratch Register 0
bit    0  Set to center
     2-4  Monitor type.
           0:  31,5kHz           Std VGA. IBM 8512,8503
           1:  31.5, 35.5 kHz    IBM 8514
           2:  31.5, 35.1 kHz    NEC 2A
           3:  31.5 - 35.5 kHz   NEC II
           4:  31.5 - 38 kHz     Multi Freq. NEC 3D
           5:  31.5 - 48 kHz     Sony CPD-1304, NEC 3FG, Nanao 9065S, 9070U
           6:  31.5 - 56.5 kHz   NEC 4D,4FG, Nanao T240i
           7:  31.5 - 64 kHz     NEC 5D,5FG/6FG, Nanao T560i,T660i
       7  Panel frequency

3C4h index 0Ah (R/W):  Scratch Register 1
bit    0  Display mode
       1  Disable expand
       2  Enable 16bit mode.
       4  Attribute emulation
       5  Disable bold font
       6  High refresh
       7  Voltage

3C4h index 0Bh (R/W):  VCLK 0 Numerator Register
bit  0-6  VCLK 0 Numerator bits 0-6

3C4h index 0Ch (R/W):  VCLK 1 Numerator Register
bit  0-6  VCLK 1 Numerator bits 0-6

3C4h index 0Dh (R/W):  VCLK 2 Numerator Register
bit  0-6  VCLK 2 Numerator bits 0-6

3C4h index 0Eh (R/W):  VCLK 3 Numerator Register
bit  0-6  VCLK 3 Numerator bits 0-6

3C4h index 0Fh (R/W):  DRAM Control
bit  0-1  MCLK Select: 0: 50.1 MHz, 1: 44.7 MHz, 2: 25.0 MHz, 3: 37.5 MHz
          Select 25MHz if VCLK is <= 18MHz
       2  RAS* Timing.
              0: Extended (PD on MD[27], RAS* high for 3MCLK, low for 4)
              1: Standard (RAS* high for 2.5MCLK, low for 3.5)
       5  CRT Write Buffer Depth Control
          If set there are 4 16bit levels, if clear one 16bit level.
       7  CRT Refresh disabled if set (LCD mode)
          (5434)

3C4h index 10h (R/W):  HW Cursor X-position
bit  0-7  When this value is written to the register, the upper 3 bits of the
          index register are taken as the low order bits of an 11 bit
          register. This is the horizontal position of the hardware cursor in
          pixels.

3C4h index 11h (R/W):  HW Cursor Y-position7
bit  0-7  When this value is written to the register, the upper 3 bits of the
          index register are taken as the low order bits of an 11 bit
          register. This is the vertical position of the hardware cursor in
          pixels.

3C4h index 12h (R/W):  HW Cursor control
bit    0  Enable the hardware cursor if set
       1  Enable Access to RAMDAC Extended Colors.
          Set to load special color values via 3C8h and 3C9h.
          When this bit is set palette entry 0 accesses the cursor background
          color and entry FFh accesses the cursor foreground color.

3C4h index 13h (R/W):  HW Cursor bitmap address
bit  0-1  Select 1 of 4 32x32 cursors
          The offset in 256 byte units within the last 16KB of video memory
          where the cursor mask and shape bitmaps are stored.
          There are two 128 byte (32x32 bits) bitmaps stored in video memory.
          The appearance of the cursor at each pixel is determined by a
          combination of the corresponding pixels from the first and second
          bitmap:
            1st: 2nd:
             0    0     The original screen pixel is shown (invisible cursor)
             0    1     The pixel is shown in the cursor background color.
             1    0     The pixel is shown as the inverse of the original
                        screen pixel (XOR cursor)
             1    1     The pixel is shown in the cursor foreground color.

3C4h index 14h (R/W):  Scratch-Pad 2
bit  0-7  Reserved

3C4h index 15h (R/W):  Scratch-Pad 3
bit  0-7  Reserved

3C4h index 16h (R/W):  Miscellaneous
bit  0-7  Reserved

3C4h index 19h (R/W):  Scratch-Pad 4
bit  0-7  Reserved

3C4h index 1Ah (R/W):  Miscellaneous
bit    4  Enable 64x64 H/W cursor
       5  Enable Improved cycle latency
       6  Select dual-scan color panel
       7  Select one DRAM refresh per line

3C4h index 1Bh (R/W):  VCLK 0 Denominator & Post
bit    0  VCLK 0 Post Scalar bit. Divide clock by 2 if set
     1-5  VCLK 0 Denominator Data
Note: The clock is (14.31818MHz * numerator (index 0Bh))/Denominator.
      Divide by 2 if the Post Scalar bit is set.
      3C2h bits 2-3 selects between VCLK0, 1, 2 and 3
      The 5420 can not handle frequencies above 75.2 MHz

3C4h index 1Ch (R/W):  VCLK 1 Denominator & Post
bit    0  VCLK 1 Post Scalar bit. Divide clock by 2 if set
     1-5  VCLK 1 Denominator Data
Note: See index 1Bh for the frequency calculation

3C4h index 1Dh (R/W):  VCLK 2 Denominator & Post
bit    0  VCLK 2 Post Scalar bit. Divide clock by 2 if set
     1-5  VCLK 2 Denominator Data
Note: See index 1Bh for the frequency calculation

3C4h index 1Eh (R/W):  VCLK 3 Denominator & Post
bit    0  VCLK 3 Post Scalar bit. Divide clock by 2 if set
     1-5  VCLK 3 Denominator Data