cirrus.txt

比较详尽的VGA端口寄存器的文档

       6  5v/3v Monitor Sense Select. 5V if set, 3.3V if clear
       7  Select OSC as SQCLK.
          If set SQCLK is derived from OSC, if clear from an input

3CEh index 9Dh (R/W):  Configuration 1 Register                    (5410 only)
bit  0-1  Bus Type
       6  Use External SQCLK Synthesizer
       7  Use External VDCLK Synthesizer

3CEh index 9Eh (R/W):  Frame-Accelerator Even Frame Start Addr          (6440)
bit  0-7  Frame-Accelerator Even Frame Start Address bits 12-19
Note: should not be modified by applications.

3CEh index 9Eh (R/W):  Display Memory Configuration High                (5410)
bit  0-2  SQCLK Frequency
     3-4  DRAM Width
     5-7  DRAM Depth

3CEh index 9Fh (R/W):  Frame-Accelerator Odd Frame Start Addr           (6440)
bit  0-7  Frame-Accelerator Odd Frame Start Address bits 12-19
Note: should not be modified by applications.

3CEh index 9Fh (R/W):  Display Memory Configuration Low                 (5410)
bit    0  DMCR0
     1-3  Display Memory Bus Width
     4-6  Display Memory Bus Depth

3CEh index A0h (R/W):  Bus Interface Unit Control
bit    0  Disable BIOS ROM (ignore accesses to C0000h-C7FFFh) if set
       1  Disable Sleep Mechanism if set
       2  (not 5410) Enable Write Protect RAMDAC if set
       3  MEMCS16* Mode Select. If set A0000h-C7FFFh is decoded as 16bit, if
          clear only the range used for the current mode is decoded as 16bit.
       4  Enable 16bit Memory if set
       5  (6440) Enable 16bit I/O if set
       6  (5410) Enable 16bit I/O
          (not 5410) Disable CPU Address Scramble (3C4h index 3 bits 1,3)
            if set
       7  (5410) Enable 16bit Interface in Planar Modes

3CEh index A1h (R/W):  Three-State & Test Control
bit    3  All other Output & I/O pins Three-State Control. If set all output
          and I/O pins are three-stated
       5  If set the CRTC Offset (3d4h index 13h) and Display Start Address
          (3d4h index 0Ch,0Dh).are multiplied with 4.
          Set in extended 256color modes.
       7  (not 5410) Disable I/O Read if set. Must be set to access the
            CL-GD6340.
Note: The undefined bits should be set to 0 when writing this register.

3CEh index A2h (R/W):  BIOS Page Selection                          (not 5410)
bit  0-2  Select ROM BIOS Page

3CEh index A6h (R/W):  Wait State Controls
bit    0  Disable Memory Write Wait State Control. If set the READY* is forced
          to synchronize with the CPU clock which adds one clock period.
       1  Disable I/O Read Wait State if set, if clear one SQCLK period is
          added.
       2  Enable 0 Wait State for Memory Write if set
       3  (not 6440) Disable RAMDAC I/O Wait State
       4  Disable I/O Write Wait State if set,  if clear one SQCLK period is
          added for I/O writes.
       6  (not 5410) BIOS Wait-State Control. 0 Wait States if set
       7  (R) Bus width Status Bit. 16bit if set, 8bit if clear

3CEh index A7h (R/W):  General Programmable I/O Port Control        (not 5410)
bit    0  (6440) Output pin PO0 (pin 103) Control
       1  Output pin PO1 (pin 104) control
       2  (6410,20,40) Output pin PO2 (pin 105) Control
       3  (6440) Output pin PO3 (pin 106) Control
       4  (6440) Write Protect 3CEh index 0Dh if set
       6  (6440) Enable PO[3:0]. If set pins 103-106 is configured as outputs

3CEh index A9h (R/W):  Bus Interface Unit Cache Control
bit    0  (5410) Enable Read from Write FIFO
       1  Enable Cache Read if set
       2  (6440,5410) Enable Write Plane-Select Compaction in Write Mode 0 if
          set
       3  (6410,12,5410) Enable Write-Overwrite Compaction in modes 2,3
       4  (5410) Enable 16bit Peripheral in Planar Modes
     5-6  Internal BIU Timing to control delays

3CEh index AAh (R):  Design Revision
bit  0-3  Design Revision
     4-7  Design ID (Major version):
            4:  CL-GD6440
            5:  CL-GD6412
            6:  CL-GD5410
            7:  CL-GD6420
            8:  CL-GD6410

3CEh index ABh (R/W):  Mask Revision                                (not 5410)
bit  0-7

3CEh index AEh (R/W):  Alternate Extension Decode High        (5410,6412 only)
bit  0-7  Bits 8-15 of the value. Bits 0-7 are in index AFh

3CEh index AEh (R/W):  Color Expansion Pixel Mask                  (6440 only)
bit  0-7

3CEh index AFh (R/W):  Alternate Extension Decode Low         (5410,6412 only)
bit  0-7  Bits 0-7 of the value. Bits 8-15 are in index AEh

3CEh index B0h (R/W):  Color Expansion Control                     (6440 only)
bit    0  Enable Color Expansion if set (enables bit 2 ??)
       1  Enable by 8 Address Mode if set. The CPU addresses are shifted left
          by 8
       2  Write Mode 4/5 Control. If set write mode 4 is selected where the
          foreground color is written to each pixel where the corresponding
          bit of the CPU data is set, if clear write mode 5 is selected where
          each pixel is written with the foreground or background color
          depending on the corresponding bit in the CPU data byte.
       4  Enable Enhanced Writes for 16bit pixels if set. The CPU addresses
          are shifted left 4 bits so that each bit corresponds to one pixel.
          16 bytes can be copied by one CPU byte.

3CEh index B1h (R/W):  Linear Address Map                          (6440 only)
bit  0-3  Linear Address Map. Selects the address of the 1MB linear video
          buffer. 0=no linear map, 1-15 map on corresponding MB boundary.

3CEh index B2h W(R/W):  Foreground Color for Color Expansion       (6440 only)
bit 0-15  Foreground color for color expansion in Write mode 4 and 5

3CEh index B4h W(R/W):  Background Color for Color Expansion       (6440 only)
bit 0-15  Foreground color for color expansion in Write mode 5

3CEh index BAh (R/W):  Scratch Pad 0
bit  0-7

3CEh index BBh (R/W):  Scratch Pad 1
bit  6-7  Video Memory:  0: 256K, 1: 512K, 2: 768K, 3: 1024K

3CEh index BCh (R/W):  Scratch Pad 2
bit  0-7

3CEh index BDh (R/W):  Scratch Pad 3
bit  0-7

3CEh index BEh (R/W):  Scratch Pad 4
bit  0-7

3CEh index BFh (R/W):  Scratch Pad 5
bit  0-7

3CEh index C0h (R/W):  Attribute and Graphics Control
bit    0  (not 5410) Enable Foreground Enhancement if set. The intensity bit
          of the foreground color is XOR, except if the color is 0 or 8.
       1  Bypass Internal Palette if set.
       2  (6412) Enable 4bit Single-Scan Monochrome Panel Support
          (6440) Attribute Emulation. If set the text mode attributes will be
           changes as follows:
             ForeGround shade > BackGround shade
                      ForeGround = White and BackGround = Black
             ForeGround shade < BackGround shade
                      ForeGround = Black and BackGround = White
          (5410) Disable 3C0h index 14h
       3  Enable Background Color Enhancement if set.

3CEh index C1h (R/W):  Cursor Attributes
bit    0  Enable Cursor Blinking if clear
     1-2  Cursor Blinking Rate
       3  Cursor Mode. Invert if set, replace if clear
       4  Invert Border Color if set
       5  (not 5410) Cursor Color Control. If set the cursor is forced to
          black and white

3CEh index C2h (R/W):  Graphics Controller Memory Latch 0
bit  0-7

3CEh index C3h (R/W):  Graphics Controller Memory Latch 1
bit  0-7

3CEh index C4h (R/W):  Graphics Controller Memory Latch 2
bit  0-7

3CEh index C5h (R/W):  Graphics Controller Memory Latch 3
bit  0-7

3CEh index C8h (R/W):  RAMDAC Control
bit    1  (6410,12,40) Select 16color Extended mode (Packed-pixel) if set
       2  (6440) Enable 256 Color Modes if set (not 320x200 ?)
       5  Enable Force Blank to RAMDAC if set
       6  (6440) Grey Scale Data from Attribute registers if set
Note: The undefined bits should be set to 0 when writing this register.

3CEh index C9h (R/W):  Graphics and Attribute Test
bit  0-2  (5410) GAT bits 0-2
       3  (6410,12,40,5410) Enable 9dot Font if set. The ninth bit is taken
          from plane 3 bit 7.
       4  (not 6440) Three-State Pixel data & VDCLK
       5  (6440) LSB value of Red and Blue and Green for HiColor modes.
          In HiColor modes (bit 7 set) this bit is used as the LSB of the red,
          blue and green (if bit 6 is clear) .
          (5410) Red/Blue LSB
       6  (6440) Select 15/16bit color. If set 16bit, if clear 15bit.
          This bit is cleared when bit 7 is set
          (5410) Green LSB
       7  (6440,5410) Enable Direct (15/16bit) Color if set

3CEh index D0h (R/W):  Flat Panel Column Offset                     (not 6440)
bit  0-7  Bit 8 is in index D4 bit 0.

3CEh index D1h (R/W):  Flat Panel Horizontal Displayed              (not 6440)
bit  0-7  Bit 8 is in 3CEh index D4h bit 1

3CEh index D2h (R/W):  Flat Panel Row Offset                        (not 6440)
bit  0-7  Bits 8-9 are in 3CEh index D4 bits 2-3

3CEh index D3h (R/W):  Flat Panel Vertical Size                     (not 6440)
bit  0-7  Bits 8-10 are in 3CEh index D4h bit 4-6

3CEh index D4h (R/W):  Flat Panel Overflow                          (not 6440)
bit    0  Column Offset bit 8. Bits 0-7 are in index 60h
       1  Panel Horizontal Displayed bit 8. Bits 0-7 are in index D1h
     2-3  Row Offset Overflow bits 8-9. Bits 0-7 are in index D2h
     4-6  Panel Vertical Size Overflow bits 8-10. Bits 0-7 are in index D3h.

3CEh index D5h (R/W):  Flat Panel Attribute LCD Control             (not 6440)
bit  0-1  9 Dots Text Reduction
       2  (R) Stand-by Mode Status bit
       3  Enable Attribute Emulation
       4  Enable Extra Line Clk
       5  Enable Reverse Video in Graphics Mode
       6  Enable Reverse Video in Text Mode
       7  Enable AutoMAP

3CEh index D6h (R/W):  Flat Panel Grey Scale Offset                 (not 6440)
bit    0  Select Grey Scale offset 4 (default=13)
       1  Power Sequencing Control
       2  Power Sequencing Time Control
       4  (6420 & 6410 rev B) Enable 8bit Plasma Interface
       5  (6420 & 6410 rev B) Enable Intermodulation
       6  Enable Horizontal Stipling
       7  Enable Vertical Stipling

3CEh index D7h (R/W):  Flat Panel Retrace LLCLK Control             (not 6440)
bit  0-4  Retrace LLCLK counter

3CEh index D8h (R/W):  Flat Panel Frame Color                       (not 6440)
bit  0-3  Frame Color
       4  Enable Frame Color
       6  (6410 rev B,12,20) Enable EPSON FPLCLK

3CEh index D9h (R/W):  Flat Panel AC Modulation                     (not 6440)
bit  0-7

3CEh index DAh (R/W):  Flat Panel Display Control                   (not 6440)
bit    0  (6420, 6410 rev B) Force 32 Grey Shades
     1-2  Panel Vertical Alignment Control
     3-4  Panel Size Selection
     5-7  RGB Weight Control

3CEh index DBh (R/W):  Standby Timer Control                        (not 6440)
bit  0-5  Standby Mode Time Interval in minutes
     6-7  Standby Mode. 0: disable, 1: screen save, 2: video memory

3CEh index DCh (R/W):  Flat Panel Color Configuration               (not 6440)
bit    0  9bit Color Panel Select
       1  MOD/FPHDE/P8 pin function control. If set P8 is output,
          if clear MOD is output if bit 0 is clear, FPHDE if set

3CEh index E0h (R/W):  Flat Panel Column Offset                    (6440 only)
bit  0-7  Bit 8 is in 3CEh index E4h bit 0.
          0Ah will display the first pixel at the left edge of the display

3CEh index E1h (R/W):  Flat Panel Horizontal Displayed Size        (6440 only)
bit  0-7  The panel width in nibbles (4 pixels) (-1). 159 for 640 pixel.
          Bit 8 is in index E4h bit 1.

3CEh index E2h (R/W):  Flat Panel Row Offset                       (6440 only)
bit  0-7  Starting row from the top. Bits 8-9 are in index E4h bit 2-3

3CEh index E3h (R/W):  Flat Panel Vertical Size                    (6440 only)
bit  0-7  Number of lines (-1) in the panel.
          Bits 8-10 are in index E4h bit 4-6

3CEh index E4h (R/W):  Flat Panel Overflow                         (6440 only)
bit    0  Column Offset bit 8. Bits 0-7 are in index E0h
       1  Panel Horizontal Displayed bit 8. Bits 0-7 are in index E1h
     2-3  Row Offset Overflow bits 8-9. Bits 0-7 are in index E2h
     4-6  Panel Vertical Size Overflow bits 8-10. Bits 0-7 are in index E3h

3CEh index E5h (R/W):  Flat Panel Horizontal Centering Offset      (6440 only)
bit  0-7  Number of nibbles (4pixels) between the end of line and the start of
          the panel in 8dot video modes. Bit 8 is in index E7h bit 0

3CEh index E6h (R/W):  Flat Panel Horizontal Centering Offset-9Dot (6440 only)
bit  0-7  Number of nibbles (4pixels) between the end of line and the start of
          the panel in 9dot video modes. Bit 8 is in index E7h bit 1

3CEh index E7h (R/W):  Flat Panel Horizontal Centering Overflow    (6440 only)
bit    0  Flat Panel Horizontal Centering bit 8. Bits 0-7 are in index E5h
       1  Flat Panel Horizontal Centering (9Dot) bit 8. Bits 0-7 are in
          index E6h
       2  Flat Panel Horizontal Size Adjust. Set if the panel width is less
          than that of the CRT, clear if panel width greater or equal to the
          CRT width.

3CEh index E8h (R/W):  Flat Panel Pin Configuration                (6440 only)
bit    0  Standby/Suspend Pin Status. If set Standby Timer Status is output on
          pin 152, if clear Suspend Mode Status is output on pin 152.