cirrus.txt

比较详尽的VGA端口寄存器的文档

Note: This register resembles 3d4h index 0Ah

3CEh index 33h (R/W):  Underline Location Extension              (6410 only ?)
bit  0-4  Underline Status
       5  Count by 4 Status
       6  Double Word Status

3CEh index 34h (R/W):  Cursor Location Extension                   (5410 only)
bit  0-3  Cursor Location Address bit 16-19

3CEh index 60h (R/W):  Horizontal Total Extension
bit  0-7  Horizontal Total in character clocks (-5).
          Bit 8 is in 3CEh index 64h bit 5.
Note: The indexes 60h-64h are the actual horizontal CRTC timing controls.
      Index 83h bit 1 determines whether writes to the corresponding fields
      in the 3d4h indexes should be reflected here.

3CEh index 61h (R/W):  Horizontal Blank Start Extension
bit  0-7  Horizontal Blank Start in character clocks.
          Bit 8 is in 3CEh index 62h bit 7.

3CEh index 62h (R/W):  Horizontal Blank End Extension
bit  0-4  Horizontal Blank End Extension in character clocks
       7  Horizontal Blank Start Extension bit 8. Bits 0-7 are in index 61h.

3CEh index 63h (R/W):  Horizontal Retrace Start Extension
bit  0-7  Horizontal Retrace Start in character clocks.
          Bit 8 is in 3CEh index 64h bit 6.

3CEh index 64h (R/W):  Horizontal Retrace End Extension
bit  0-4  Horizontal Retrace End Extension in character clocks.
       5  Horizontal Total Extension bit 8. Bits 0-7 are in index 60h.
       6  Horizontal Retrace Start Extension bit 8. Bits 0-7 are in index 63h.
       7  Horizontal Blank End bit 8. Bits 0-7 are in index 62h.

3CEh index 70h (R/W):  Vertical Total Extension
bit  0-7  Vertical Total in scanlines for a frame. This is the equivalent of
          3d4h index 6. Bits 8-10 are in index 78h and 79h
Note: The indexes 70h-75h, 78h and 79h are the actual vertical CRTC timing
      controls. Index 83h bit 0 determines whether writes to the corresponding
      fields in the 3d4h indexes should be reflected here.

3CEh index 71h (R/W):  Vertical Display Enable Extension
bit  0-7  Vertical Display Enable End. This is the equivalent of 3d4h index
          12h. Bits 8-10 are in index 78h and 79h

3CEh index 72h (R/W):  Vertical Blank Start Extension
bit  0-7  Vertical Blank Start. This is the equivalent of 3d4h index 15h
          Bits 8-10 are in index 78h and 79h.

3CEh index 73h (R/W):  Vertical Blank End Extensions
bit  0-7  Vertical Blank End. This is the equivalent of 3d4h index 16h
          Bit 8 is in index 78h

3CEh index 74h (R/W):  Vertical Retrace Start Extension
bit  0-7  Vertical Retrace Start. This is the equivalent of 3d4h index 10h
          Bits 8-10 are in index 78h and 79h.

3CEh index 75h (R/W):  Vertical Retrace End Extension
bit  0-3  Vertical Retrace End. This is the equivalent of 3d4h index 11h

3CEh index 78h (R/W):  CR07 Extension
bit    0  Vertical Total bit 8. Bits 0-7 are in index 70h
       1  Vertical Display Enable bit 8. Bits 0-7 are in index 71h
       2  Vertical Retrace Start bit 8. Bits 0-7 are in index 74h
       3  Vertical Blank Start bit 8. Bits 0-7 are in index 72h
       4  Line Compare bit 8.
       5  Vertical Total bit 9
       6  Vertical Display Enable bit 9.
       7  Vertical Retrace Start bit 9

3CEh index 79h (R/W):  Vertical Overflow beyond CR07
bit    0  Vertical Total bit 10
       1  Vertical Display Enable bit 10
     2-3  Vertical Blank Start bit 9-10.
       4  Vertical Retrace Start bit 10

3CEh index 7Ah (R/W):  Coarse Vertical Retrace Skew for Interlaced
bit  0-7  Coarse Vertical Retrace Skew for Interlaced Odd Fields in
          Character Clock Periods.

3CEh index 7Bh (R/W):  Fine Vertical Retrace Skew                 (not 6440 ?)
bit  0-1  Fine Vertical Retrace Skew for Interlaced Odd Fields in Dot Clock
          Periods

3CEh index 7Ch (R/W):  Screen A Start Address Extension
bit  0-3  Screen A Start Address Extension bits 16-19.
          Bits 0-15 are in 3d4h index Ch and Dh

3CEh index 80h (R/W):  H/V Retrace Polarity Control                 (not 5410)
bit    1  (6440) Interlaced Mode Enable if set
       2  (6440) Double Character Clock for Horizontal Parameters.
          If set the Horizontal parameters will work as if they were twice
          their actual value. This bit is used in extended 256 color modes.
       4  Enable Expanded Graphics. If set a predetermined ratio (16 to 19) of
          scanlines will be replicated in graphics modes.
       5  H/V Polarity Source Control. If set bits 6-7 controls the Polarity
          signals, if clear they are controlled by 3C2h bits 6-7.
       6  Horizontal Retrace Polarity. Negative if set
       7  Vertical Retrace Polarity. Negative if set.

3CEh index 81h (R/W):  Display Mode                                 (not 6440)
bit    0  (not 5410) Select LCD Display if set, CRT if clear
       2  (6420,5410) Interlaced Mode Enable
       3  (not 5410) Enable CL-GD6340 Mode
       4  (not 5410) Select Single Scan Panel
       5  (not 5410) Enable AutoMAP
       7  (not 5410) Enable Simulscan

3CEh index 82h (R/W):  Character Clock Selection
bit  0-2  Character Clock Width. 1: 8pixels, 2:4pixels
       3  Disable SR1[0] functionality. If set the Character Clock Width will
          be determined by bits 0-2, if clear by 3C4h index 1 bit 0.
     5-6  (5410) 0: 2 CRT-clkin, 1: 1, 2: 4
       7  (6440) Enable Internal Divided by 2  if set (for Pixel Doubling)
          This divides the CRT Master clock by 2. The Flat Panel clock is not
          affected.

3CEh index 83h (R/W):  Write Control
bit    0  CRTC Vertical Parameters Write Protect. If set updates to the
          standard CRTC vertical registers (3d4h index 6,7 (bit 0,2,3,5,7),
           9 bit 5, 10h, 11h bit 0-3, 15h, 16h) will not be reflected in the
          Vertical Working Set registers (index 70h-75h,78h,79h)
       1  (6440) Horizontal Parameters Write Protect. If set updates to the
          standard CRTC horizontal registers (3d4h index 0-5) will not be
          reflected in the Horizontal Working Set registers (index 60h-64h)
          (not 6440) CRTC Display Timing Effect Write Protect
                     3d4h index 7 (bit 1,6), 9, 0Ah, 0Bh, 12h, 14h
       2  (not 6440) CRTC Vertical Display End Effect Protect
                     3d4h index 12h, 7 (bits 1,6)
       3  (not 6440) CRTC Blank Effect Protect
                     3d4h index 2, 3 bits 0-3, 5 bit 7, 7 bit 3, 9 bit 5,
                      15h, 16h
       4  (not 6440) CRTC Total/Retrace Effect Protect
       6  (not 6440) Attribute Registers Write Protect (3C0h index 0-0Fh).

3CEh index 84h (R/W):  Clock Select                                 (not 6440)
bit    1  (not 5410) Clock In Divide by 2 if set.
     2-5  Clock Select bits 0-3. If bit 7 is clear 3C3h bits 2-3 are used
          for the two low clock bits.
       7  Select bit 2-3 as clock bit 0-1 rather than 3C2h bit 2-3 if set.

3CEh index 85h (R/W):  Virtual Switch Source                       (5410 only)
     0-3  VGA Internal Switches for Analog Monitor
       4  Enable Virtual Switches

3CEh index 86h (R/W):  CRTC Test
bit  1-3  (5410) CRTC Test Bits
       4  CRTC Outputs Three-State Control. If set the HSYNMC and VSYNC
          outputs will be three-stated.
       5  (6412,40) HSYNC, VSYNC Disable. If set the HSYNC and VSYNC outputs
          are disabled and driven to 0. Used in Flat Panel mode.
Note: This register is intended for factory testing only.

3CEh index 87h (R/W):  CRTC Spare Extension      (Rev B only)
bit    1  (6412) PVSYNC Configuration
                  Pin 82:    bit 4:    bit 1:    index 8Fh bit 4:
                  LFS          0         0              0
                  FPVDE        0         0              1
                  VDE*         1         0              x
                  PVSYNC       0         1              x
       3  (6412) Enable Short VSYNC Total
       4  (NOT 5410) VDE*/LFS Configuration on pin 99.
               If set pin 99 is VDE*, if clear pin 99 is LFS
       6  (6412) Enable short HTOT (HDE+7)
       7  (6412) Enable short VTOT (VDE+4)
          (6410,20) Invert VDE* Polarity on pin 99
     6-7  (5410) Interlace Test 0-1

3CEh index 89h (R/W):  CRTC Spare 1

3CEh index 8Ah (R/W):  CRTC Spare 2

3CEh index 8Fh (R/W):  CRTC BIOS Configuration                      (not 6440)
bit  0-1  Clock Select Pin-out Configuration
       2  (6412) If set SUSPEND* input, if clear FRA8 input
       3  (6412) If set VDCLK I/O output, if clear FPVDCLK
       4  (6412) If set FPVDE output, if clear LFS output
       5  (6412) SUSPEND* pin Configuration. SUSPEND* if set, FRA8 if clear
       6  (6412) Frame Accelerator Control bit. Set if the system power down
                 the Frame Accelerator DRAM
       7  (6412,20) Enable Retrace Line Clocks

3CEh index 90h (R/W):  Display Memory Control
bit    0  Scan Line Double Control. If set each scanline will be displayed
          twice (typically 200 line modes).
       1  RAS* Precharge. Extended (4 SQCLK cycles) if clear, normal (3 SQCLK
          cycles) if set
       2  (5410) DMC2
       3  Display Memory Refresh Control Extension
     5-6  (5410) DMC5-6
       6  (6410 rev B,6420) Power Sequencing Status Bit.
Note: The undefined bits should be set to 0 when writing this register.

3CEh index 91h (R/W):  CRT Circular Buffer Policy Selection
bit    5  Reset FIFO ?
     6-7  (R)  Reserved
Note: The undefined bits should be set to 0 when writing this register.

3CEh index 92h (R/W):  Font Control
bit  0-1  Font Control Address Extension bits 16-17. Also used for Bold font
          selection ?
       3  (6410,20) Enable Software Expanded Text
       5  (not 5410) Enable Full Height Cursor. If set a full height cursor is
          displayed regardless of the Cursor Start and Cursor End (3d4h index
          Ah,Bh).
       6  (not 5410) Text Expansion Method Select. If set scanlines 0,8 and 15
          are duplicated, if clear scanline 0 is repeated twice and scanline
          15 once. This is only active if bit 7 is set.
       7  (not 5410) Enable Hardware Expanded Text. If set 16line text is
          expanded to 19 line text by the method selected by bit 6.
          This is only active in text modes.

3CEh index 93h (R/W):  Full Frame-Accelerator Bottom-half Start         (6440)
bit  0-7  Bottom Half Start Address
Note: this register should not be modified by applications.

3CEh index 93h (R/W):  CPU Interface Test Register                      (5410)
bit  6-7  CTR6-7

3CEh index 94h (R/W):  Full Frame-Accelerator Misc. Control 1           (6440)
bit    0  Frame Accelerator Selection. Full if set, Half if clear
     1-7  Should be set to 0
Note: The undefined bits should be set to 0 when writing this register.

3CEh index 95h (R/W):  CRTC Circular Buffer Delta and Burst
bit  0-3  Delta number. Should be set to 0
     4-7  Burst number. Should be set to 0

3CEh index 96h (R/W):  Display Memory Control Test Register
bit    0  Latch Monitor ID. If the screen is forced blank, and this bit is
          set and then reset the monitor ID will be latched as it is on reset.
          After one frame time without screen refresh the ID can be read from
          index 9Ch
       1  (6420) Frame Accelerator Three-State control
          (6440,5410) Video Memory Data M1D, M3D Three-State Control.
            If set the M0D and M2D busses will be three-stated
       2  Video Memory Data M0D, M2D Three-State control. If set the M0D and
          M2D busses will be three-stated
       3  Video Memory & Address Three-State control. If set the Address and
          Control pins of the Memory Sequencer (AA[0:8], AB[0:8], OE*, WE*,
          RAS* and CAS*) will be three-stated.
       4  (5410) Disable Fast-Page Mode
Note: The undefined bits should be set to 0 when writing this register.

3CEh index 97h (R):  Monitor Switches Read Back
bit    0  (6440) 14MHz Clock Source. If set a 14MHz crystal is connected
          across the XTAL1 and XTAL2 pins, if clear a 14MHz crystal is
          connected to XTAL1.
     3-7  (6440) Reserved for BIOS
     4-7  (not 6440,5410) Panel Type Switches
       7  (5410) Interlace

3CEh index 98h (R/W):  Scratch
bit  0-7  Reserved for BIOS use

3CEh index 99h (R):  Configuration Register 0
bit    0  BIOS address. If bits 1-2 are 0 (Local Bus) this is the data bus
          width (set for 32bit, clear for 16) if bits 1-2 are 2 (ISA bus) this
          is the BIOS support (C000h on adapter with BIOS support if clear,
          C0000h or E0000h on motherboard with no BIOS support if set).
       1  (5410) CPU Bus Type. 0: ISA, 1: MCA
     1-2  (6440) CPU Bus Type. 0: Local Bus, 1: PI bus, 2: ISA bus
       2  (not 6440) Disable VGA address space
       3  Sleep at 46E8h if set, 3C3h if clear
       4  BIOS is 16bit if set, 8bit if clear
       5  (6440) VGA Address space. If set the VGA I/O addresses are decoded
          at xxx instead of 3xx and yxxx instead of Axxx or Bxxx for video
          memory
       6  (6440) Disable ST100 Effect if set
       7  (6440) CPU clock select/ISA I/O select. If bits 1-2 are 0 (Local
          Bus) this is the CPU Clock Select (set x2 clock and CPURESET pin
          activated, clear for x1 clock and CPURESET pin deactivated) if bits
          1-2 are 1 (PI bus) this is the I/O select (I/O through the PI bus if
          clear, I/O through ISA bus if set).

3CEh index 9Ah (R/W):  Video Memory Configuration
bit  0-7  (not 6440,5410) Reserved. should be programmed to 0.
     0-2  (6440) Memory Width.
            0: 32bit Memory bus with 4 CAS (8 256kx4 or 2 256kx16)
     6-7  (5410) RAMDAC Select 0-1

3CEh index 9Bh (R/W):  Miscellaneous Pin Configuration
bit    0  Enable Sequencer Clock (SQCLK) inversion if set
       1  On Chip Monitor Sense Enable if clear, disable if set ?
     3-4  (not 6440,5410) INTERNAL/MOD Pin Configuration.
                           0: INTERNAL, 1: MODULATION
     5-6  (not 6440,5410) LLCLK/DE Configuration.
                      0: LLCLK, 1: DE (for GD6340),
                      3: Pins 98/99=PHSYNC/PVSYNC
       7  (6412) Paged BIOS Disable.
                 If set pins 62-64 are TIMER*, PO1 and SSCLK
                 if clear pins 62-64 are BIOS address bit 13-15
Note: The undefined bits should be set to 0 when writing this register.

3CEh index 9Ch (R):  PS/2 Monitor ID Read-back
bit  5-7  Monitor ID. 2: 8514, 5: 8503, 6: 8512/8513, 7: no monitor

3CEh index 9Dh (R/W):  Miscellaneous Configuration 2               (6412 only)
bit    0  FPVDCLK Delay. If set delay FPVDCLK by 1/2 Video Clock (VDCLK)
       1  Select OE* Delay. If set OE* is delayed by one Memory Clock (SQCLK)