cirrus.txt

比较详尽的VGA端口寄存器的文档

  Cirrus Logic

    CL-GD 410/420     (Also known as Video7 OEM)
    CL-GD 510/520     Flat Panel/LCD
    CL-GD 610/620     Flat Panel/LCD

    CL-GD 5320

The 64xx Flat Panel family:

    CL-GD 5410
    CL-GD 6410    160pin  Flat Panel/LCD controller. 256k no banks.
                          Supports 512 color TFT and 64 shades on mono STN
    CL-GD 6412    160pin  As 6410 but mixed 3.3V and 5V
    CL-GD 6420    160pin  As 6410 but 1MB. Supports 185000 colors on TFT
                          and 64 shades on mono STN, color TFT
    CL-GD 6416
    CL-GD 6440    208pin  As 6420 but mixed 3.3V and 5V. Supports 8 and 16bit
                          single- and dual-scan color STN, 9,12,15 and 18bit
                          color TFT panels.
    CL-GD 6450

The 54xx Super VGA family:

    CL-GD 5401        AVGA 1. No banks
    CL-GD 5402        AVGA 2.
Note: the 5401 and 5402 are sometimes sold as the Acumos AVGA1 and 2.
    CL-GD 6205    160pin  Flat Panel/LCD. Mixed 3.3 and 5V. always 512KB
                          64 shades on mono STN. Color TFT support
    CL-GD 6215    160pin  As 6205 with Local bus and PI support
    CL-GD 6225    160pin  As 6215 with single-scan color STN support
    CL-GD 6235    160pin  As 6235 with dual-scan color STN support
    CL-GD 6245

    CL-GD 5420    160pin  1MB 15/16 bit DAC.
    CL-GD 5422    160pin  1MB 15/16/24bit DAC
    CL-GD 5424    160pin  As 5422 with Local bus support
    CL-GD 5426    160pin  As 5424 with 2MB and BitBLT
    CL-GD 5428    160pin  As 5426 with faster BitBLT
    CL-GD 5429    160pin  As 5428 with Memory Mapped I/O
    CL-GD 5430    208pin  2MB  "Alpine" 64bit memory and 32bit BitBLT engine
                               accelerates 8/16 it pixels
    CL-GD 5432        "Alpine" 32bit version
    CL-GD 5434    208pin  4MB  "Alpine" 64bit memory and BitBLT engine.
                               accelerates 8/16/24/32 bit pixels
    CL-GD 5452/3  208pin  4MB  64bit Highres truecolor controller
                               Linedraw. 2 chip set (5453 is the DAC).
    CL-GD 547x    future 3d accelerator chip

    CL-GD 7541    Nordic Lite. 2Mb LCD controller
    CL-GD 7542    Nordic       2Mb LCD controller
    CL-GD 7543    Viking       2Mb LCD controller?

Not too sure that the CL-GD5432, CL-GD6416 really exist

The 54xx and 64xx series have a built in RAMDAC. 8 bit for the 5401/5402 and
 6410/12/20, 15/16bit for the 5420 and 6440 and 15/16/24 bit for the 5422-3x.
The 54xx, 62xx and 6440 have built-in clock generator


Support Chips:
    CL-GD 6340    100pin  (Peacock) Color LCD Panel Driver. Supports 8, 512
                             and 4K color panels. Onboard RAMDAC
    CL-GD 5453    208pin  Palette DAC for the CL-GD5452



The 5xx/6xx Flat Panel family:
This family strongly resembles the early Video 7 chips. Apparently Cirrus
supplied at least one of the early Video 7 chips (Video7 OEM).

3C4h index  6  (W):
bit 0-7  Writing ("Eagle ID" rol 4) will disable extensions.
         Writing "Eagle ID" will enable.
         Reading will return 0 if extensions are disabled, 1 if enabled
The "Eagle ID" is read from 3d4h index 1Fh

3C4h index 80h (R/W):  Miscellaneous Control 1

3C4h index 81h (R/W):  Graphics Position 1

3C4h index 82h (R/W):  Graphics Position 2

3C4h index 83h (R/W):  Attribute Controller Index

3C4h index 84h (R/W):  Write Control

3C4h index 85h (R/W):  Timing Control

3C4h index 86h (R/W):  Bandwidth Control

3C4h index 87h (R/W):  Miscellaneous Control 2

3C4h index 88h (R/W):  Horizontal Sync skew

3C4h index 89h (R/W):  CGA, HGC Font Control

3C4h index 8Ah (R/W):  Reserved

3C4h index 8Bh (R/W):  Screen B preset row scan

3C4h index 8Ch (R/W):  Screen B start address high

3C4h index 8Dh (R/W):  Screen B start address low

3C4h index 8Eh (R):  Version Code

3C4h index 8Fh (R):  Version Code

3C4h index 90h (R/W):  Vertical Retrace Start

3C4h index 91h (R/W):  Vertical Retrace End

3C4h index 92h (R/W):  Lightpen High

3C4h index 93h (R/W):  Lightpen Low

3C4h index 94h (R/W):  Pointer Pattern Address High
bit  0-7  Start address of the hardware cursor map in units of 256 bytes
          within the last 64K of video memory

3C4h index 95h (R/W):  Cursor Height Adjust

3C4h index 96h (R/W):  Caret Width

3C4h index 97h (R/W):  Caret Height

3C4h index 98h (R/W):  Caret Horizontal Position High

3C4h index 99h (R/W):  Caret Horizontal Position Low

3C4h index 9Ah (R/W):  Caret Vertical Position High

3C4h index 9Bh (R/W):  Caret Vertical Position Low

3C4h index 9Ch M(R/W):  Pointer Horizontal Position
bit 0-10  Cursor X position from left

3C4h index 9Eh M(R/W):  Pointer Vertical Position High
bit  0-9  Cursor Y position from top

3C4h index A0h (R/W):  Graphics Controller Memory Latch 0

3C4h index A1h (R/W):  Graphics Controller Memory Latch 1

3C4h index A2h (R/W):  Graphics Controller Memory Latch 2

3C4h index A3h (R/W):  Graphics Controller Memory Latch 3

3C4h index A4h (R/W):  Clock Select

3C4h index A5h (R/W):  Cursor (Caret and pointer) Attribute
bit    7  Set to enable hardware cursor

3C4h index A6h (R/W):  Internal Switch Source

3C4h index A7h (R/W):  Status Switch Control

3C4h index A8h (R/W):  NMI Mask 1

3C4h index A9h (R/W):  NMI Mask 2

3C4h index AAh (R/W):  Reserved

3C4h index ABh (R):  NMI Status 1

3C4h index ACh (R):  NMI Status 2

3C4h index ADh (R/W):  256 Color mode Page Control

3C4h index AEh (R):  NMI data cache (Four 24 bit words)

3C4h index AFh (R/W):  Active Adapter State

3C4h index B0h..BFh (R/W):  Scratch Registers

3C4h index C0h..FFh (R/W):  Reserved

3d4h index 0Ch (R/W):  Screen A start address Hi
Must be cleared before the Eagle ID Register (3d4h index 1Fh) can be read.

3d4h index 1Fh (R):  Eagle ID register
bit 0-7  Eagle ID.  Used for test of 3C4h index 6.
         Reading this register will return the content of 3d4h index 0Ch XORed
         with the Eagle ID value.
         ECh for CL-GD 510/520, CAh for 610/620. EAh for Video7 boards.

Memory locations:

$C000:$6  2 bytes  'CL'  if Cirrus Bios

  Modes for the CL-GD510/520:

  40h T  100   30
  41h T  100   50
  42h T  100   60
  50h T  132   30
  51h T  132   50
  52h T  132   60
  53h T   80   60
  62h G  640  450  16
  63h G  720  540  16
  64h G  800  600  16


  Other sources claim:

  15h T  132   25   2 (8x14)
  16h T  132   44   2 (8x8)
  18h T  132   30   2 (8x)
  1Eh T  132   25  16 (8x8)
  1Fh T  132   25  16 (8x14)
  20h T  132   44  16 (8x8)
  22h T  132   30  16 (8x)
  31h T  100   37   2
  40h G  720  540  16 PL4
  50h G  640  400 256 packed
  51h G  512  480 256 packed    Note: not supported in all BIOS'es
  63h G  720  540  16 PL4
  64h G  800  600  16 PL4
  6Ah G  800  600  16 PL4

  Mode 50h and 51h use a special system where four pixels are stored at the
  same byte address in plane 0,1,2 and 3 respectively.




GD6349  (Peacock) Color LCD controller:

3C4h index E0h (R/W):  Enable Readback Register
bit  0-7  0: Turn Readback off, F0h: Enable Readback (ALLSET)

3C4h index E9h (R):  Identification Register
bit 4-7  Reads alternatingly as 7 and 8.



GD5410, 64xx series:

100h (R/W):  CL-GD6440 Power Up Configuration                    (6440 only ?)
bit    0  Local Bus width. Set for 32bit, clear for 16 bit (386SX)
     1-2  CPU Bus Type.
       3  Sleep address. Set for 46E8h, clear for 3C3h
       7  Local Bus Clock. Set for x2 clock, clear for x1 clock.
Note: This register can be accessed even when the CL-GD6440 is in sleep mode.

3CEh index 0Ah (R/W):  Extension Control
bit  0-7  Write ECh to enable extensions, CEh to disable.
          Reads as 1 if enabled, 0 if not.

3CEh index 0Bh (R/W):  Attribute Controller Index (ARX) r/w with toggle
bit  0-4  Attribute Register Index
       5  (not 6440 ?) Enable Video
       7  Toggle ARX to Data. If set the Attribute register is in Data mode,
          if clear in Index mode

3CEh index 0Ch (R/W):  CR11 bit 7 at Extension
bit    7  Write Protect 3d4h index 0-7 if set
          Can be used to break the deadlock between 3d4h index 3 bit 7 and
          3d4h index 11h bit 7 as this it can always be changed.

3CEh index 0Dh (R/W):  CPU Base Address Control                     (not 6410)
bit    0  Enable Page Remapping if set
       1  Enable 64K Remapping page size if set, 32K if clear
       2  If set use both 3CEh index 0Eh and 0Fh, if set use only index 0Eh:
          Bit 2  Bit 1     Index 0Eh       Index 0Fh
            0      0     A0000h-A7FFFh     Not used
            0      1     A0000h-AFFFFh     Not used
            1      0     A0000h-A7FFFh   A8000h-AFFFFh
            1      1     A0000h-AFFFFh   B0000h-BFFFFh
          Note: for bit 1&2 both set (dual 64k maps) 3CEh index 6 bits 2-3
                should be set to 0 to allow 128k video buffer.
       4  (6440) Enable Linear Addressing if set. See index B1h for details
       7  (not 6440) Enable I/O Ext Addr Remapping
Note: this register can be locked by 3CEh index A7h bit 4.

3CEh index 0Eh (R/W):  CPU Base Address Mapping Register A          (not 6410)
bit  0-7  Bank number in 4K units for accesses to the A0000h-A7FFFh (index Dh
          bit 1 clear) or A0000h-AFFFFh (index Dh bit 1 set) range.

3CEh index 0Fh (R/W):  CPU Base Address Mapping Register B          (not 6410)
bit  0-7  Bank number in 4K units. If 3CEh index 0Dh bit 2 is set this
          register is used for accesses to the A8000h-AFFFFh (index Dh
          bit 1 clear) or B0000h-BFFFFh (index Dh bit 1 set) range.

3CEh index 30h (R/W):  Cell High Extension                       (6410 only ?)
bit  0-4  Cell High Status
       5  Vertical Blank Start bit 9 Status
       6  Line Compare bit 9 Status
       7  Scan Double Status
Note: This register resembles 3d4h index 9 ??

3CEh index 31h (R/W):  Cursor Start Extension                    (6410 only ?)
bit  0-4  Cursor Start Status
       5  Disable Cursor Status
Note: This register resembles 3d4h index 0Ah

3CEh index 32h (R/W):  Cursor End Extension                      (6410 only ?)
bit  0-4  Cursor End Status
     5-6  Cursor Skew Status