ncr.txt

比较详尽的VGA端口寄存器的文档

          Retrace register (3d4h index 0). Bit 8 is in index 30h bit 3.
     4-5  Horizontal Blank End bits 6-7. Bits 6-7 of the Horizontal Blanking
          End register (3d4h index 3).
     6-7  Horizontal Retrace End bits 5-6. Bits 5-6 of the Horizontal Retrace
          register (3d4h index 5).

3d4h index 33h (R/W):  Extended Vertical Timings                   (22E+ only)
bit    0  Vertical Total bit 10.  Bit 10 of the Vertical Total register (3d4h
          index 6). Bits 8 and 9 are in 3d4h index 7 bits 0 and 5.
       1  Vertical Display Enable End bit 10. Bit 10 of the Vertical Display
          End register (3d4h index 12h). Bits 8 and 9 are in 3d4h index 7 bits
          1 and 6
       2  Vertical Blank Start bit 10. Bit 10 of the Vertical Blank Start
          register (3d4h index 15h). Bit 8 is in 3d4h index 7 bit 3 and bit 9
          in 3d4h index 9 bit 5
       3  Vertical Retrace Start bit 10. Bit 10 of the Vertical Retrace Start
          register (3d4h index 10h). Bits 8 and 9 are in 3d4h index 7 bits 2
          and 7
       4  Line Compare bit 10. Bit 10 of the Line Compare register (3d4h index
          18h). Bit 8 is in 3d4h index 7 bit 4 and bit 9 in 3d4h index 9 bit 6
     5-6  Vertical Blank End bits 8-9. Bits 8-9 of the Vertical Blank End
          register (3d4h index 16h).
       7  Vertical Retrace End bit 4. Bit 4 of the Vertical Retrace End
          register. Bits 0-3 are in 3d4h index 11h bits 0-3.

3d4h index 34h (R/W):  Monitor Power Management                      (32 only)
bit    0  Set HSync low
       1  Set HSync high
       2  Set VSync low
       3  Set VSync high


The Memory Mapped Registers (Accelerator Control Menu - ACM) can only be
accessed when 3C4h index 30h bit 0 is set. The base address of the ACM
registers are defined in 3C4h index 31h-33h.

Memory 00h W(R/W):  Primary Offset                                   (32 only)
bit 0-15  If 3C4h index 30h bit 2 is set this is the Primary Host Offset
          register (3C4h index 18h-19h)

Memory 04h W(R/W):  Secondary Offset                                 (32 only)
bit 0-15  If 3C4h index 30h bit 2 is set this is the Primary Host Offset
          register (3C4h index 1Ch-1Dh)

Memory 09h (R/W):  Mode Control Register                             (32 only)
bit  0-1  DRAM Address Configuration. These bits can only be modified
          if 3C4h index 5 bit 2 is set.  0: 64Kx, 1: 256Kx, 3: 1Mx
       2  Secondary Offset Enable. If this bit and bit 4 are set all read
          operations are modified by multiplying the Secondary Host Offset by
          16 and adding the result to the host address.
       4  Extended Memory Enable. If set extended memory is enabled.
     5-7  Primary/Secondary Read/Write Select.
            0:  Write to Primary, Read from Secondary
            1:  Write to Primary, Read toggles from Secondary to Primary ?
            2:  Primary at A0000h-AFFFFh, Secondary at B0000h-BFFFFh.
                Both Read/Write
            3:  Read and Write to Secondary only
Note: This is the Extended Memory Enable register (3C4h index 1Eh).

Memory 0Ch W(R/W):  Cursor X Position Register                       (32 only)
bit 0-10  If 3C4h index 30h bit 1 is set this is the Cursor X Position
          registers (3C4h index 0Dh and 0Eh)

Memory 0Eh W(R/W):  Cursor Y Position Register                       (32 only)
bit 0-11  If 3C4h index 30h bit 1 is set this is the Cursor Y Position
          registers (3C4h index 0Fh and 10h)

Memory 30h (R/W):  BLT Start Register                                (32 only)
bit    0  Start/Stop. Set to start a BLT operation, clear to stop the
          current operation
       1  Text BLT. Set for Text Mode BLTs, clear for standard BLTs
       2  BLT Completed Interrupt. If set causes an interrupt when the
          Accelerator engine has completed an operation. The interrupt is
          cleared when a 0 is written to this bit.
       3  Write FIFO Empty Interrupt. If set enables an interrupt when the
          Write FIFO goes empty

Memory 32h (R):  BLT Status Register                                 (32 only)
bit    0  Ready. If clear the engine is busy, if set the operation has
          finished and the parameters can be updated.
       1  Error. If set indicates that an illegal BLT operation was entered.
          This bit is cleared when a new operation is started.
       2  BLT Done Interrupt Status. Set when an interrupt has been generated
          due to a BLT Done condition.
       3  Write FIFO Near Empty Interrupt. Set if an interrupt has been
          generated due to a Write FIFO Near Empty condition.
       4  Write FIFO Full. Set when the Write FIFO is full

Memory 34h W(R/W):  BLT Control Register                             (32 only)
bit    1  Color Compare Invert. If clear color match operations return 1 for
          the pixels which match the reference color and 0 for those that
          don't, if set this is reversed.
       3  Map Width. If set the data transferred when either the Source or
          Destination data is in system memory is padded or truncated to
          achieve word aligned data.
       4  Large Pattern Enable. If clear 8x8 pixel patterns are used, if set
          16x16 patterns are used for 256 color modes.
       5  Transparency Enable. If set enables background transparency for
          color expand operations.
       6  Vertical Direction. The Blit direction is "down" (increasing Y) if
          set, "up" (decreasing Y) if clear
       7  Horizontal Direction. The Blit direction is "left" (increasing X) if
          set, "right" (decreasing X) if clear.
       9  Color Fill Enable. If set the operation is a solid fill and only one
          pixel of the pattern data need be read.
      10  Color Compare Enabled if set
      11  Color Expand Enable. If set the source data is monochrome and is
          replaced with fore/background data in the full color depth
      12  Destination Address Mode. If set the source data is stored in
          linear format, if clear it is stored in rectangular format.
      13  Source Address Mode. If set the destination data is stored in
          linear format, if clear it is stored in rectangular format.
      14  Destination Location. If set the Destination is in the frame
          buffer, if clear the destination data is transferred to the system
          memory via the ?read? FIFO.
      15  Source Location. If set the Source data comes from the frame buffer,
          if clear the system supplies the Source data

Memory 38h (R/W):  Pattern X Rotation                                (32 only)
bit  0-3  The Horizontal Pixel alignment of the pattern

Memory 39h (R/W):  Pattern Y Rotation                                (32 only)
bit  0-3  The Vertical Pixel alignment of the pattern

Memory 3Ah (R/W):  Raster Opcode                                     (32 only)
bit  0-7  The raster opcode. See MS-Windows trinary raster codes for the full
          list. CCh is copy source -> Destination

Memory 3Ch W(R/W):  Bitmap Dimension Width                           (32 only)
bit 0-11  Bitmap Width. The width of the Source and Destination bitmaps in
          pixels

Memory 3Eh W(R/W):  Bitmap Dimension Height                          (32 only)
bit 0-11  Bitmap Height. The height of the Source and Destination bitmaps in
          pixels. For Text BLTs this is the character cell height

Memory 40h D(R/W):  Destination Register                             (32 only)
bit  0-2  Bit position for monochome bitmaps. For Color Compare to Memory BLTs
          this field specifies the initial bit alignment of the Destination
          bitmap
    3-24  Destination Address. This is the address of the starting corner of
          the Destination Bitmap

Memory 44 D(R/W):  Source Register                                   (32 only)
bit  0-2  Bit position for monochome bitmaps. For Color Expand BLTs this field
          specifies the initial bit alignment of the Source bitmap
    3-24  Source Address. This is the address of the starting corner of the
          Destination Bitmap

Memory 48h D(R/W):  Pattern Register                                 (32 only)
bit  0-2  Bit offset, must be 0
    3-24  Pattern Address. This is the address of the starting corner of
          the Pattern. The address must be DWORD aligned.

Memory 4Ch D(R/W):  Foreground Color Register                        (32 only)
bit 0-23  The foreground color

Memory 50h D(R/W):  Background Color Register                        (32 only)
bit 0-23  The Background Color.


  ID NCR VGA:

  if testinx2($3C4,5,5) then
  begin
    wrinx($3C4,5,0);   {Lock extensions}
    if not testinx($3C4,$10) then
    begin
      wrinx($3C4,5,1);
      if testinx($3C4,$10) then
        case rdinx($3C4,8) div 16 of
          0:NCR 77C22;
          1:NCR 77C21;
          2:if (rdinx($3C4,8) and 15)<8 then NCR 77C22E
                                        else NCR 77C22E+;
          3:NCR 77c32BLT;
        end;
    end;
  end;


  Video Modes:

  40h G 1600 1200  16  PL4                    32BLT
  41h G 1600 1200 256  P8                     32BLT
  50h G  640  480 16m  P24                    32BLT
  51h G  800  600 16m  P24                    32BLT
  54h T  132   50  16  (8x8)
  55h T  132   25  16  (8x16)
  56h T  132   50   4  (8x8)
  57h T  132   25   4  (8x16)
  58h G  800  600  16  PL4
  59h G  800  600   2
  5Ah G 1024  768   2
  5Bh G 1024  768  16  PL4    (Interlaced)
  5Ch G  800  600 256  P8
  5Dh G 1024  768  16  PL4
  5Eh G  640  400 256  P8
  5Fh G  640  480 256  P8
  61h G 1024  768 256  P8     (Interlaced)    22E !!
  62h G 1024  768 256  P8                     22E !!
  67h G 1280 1024  16  PL4    (Interlaced)    22E !!
  6Ah G 1280 1024 256  P8     (Interlaced)    22E !!
  6Bh G 1280  960 256  P8                     22E !!
  6Ch G 1280 1024  16  PL4                    32BLT
  70h G  640  480 32k  P15                    22E !!
  71h G  800  600 32k  P15                    22E
  72h G 1024  768 32k  P15                    32BLT
  78h G  640  480 64k  P16                    22E
  79h G  800  600 64k  P16                    22E
  7Ah G 1024  768 64k  P16                    32BLT

Note: Modes above 57h may require a driver (setmode.sys) to be loaded
      depending on BIOS version.