ncr.txt

比较详尽的VGA端口寄存器的文档

           maximum system performance.
          (32 only) Enable Palette Shadowing. If set writes to the Palette RAM
           are executed, but the LDEV/ and LRDY/ signals are not asserted,
           allowing other devices to respond to the operation
       4  (22E+) Enable CPU Bus. Set for Local Bus, clear for AT and MCA bus
          (32 only) Shadow All Writes. If set all write operations are
           executed, but the LDEV/ and LRDY/ signals are not asserted,
           allowing other devices to respond tp the operation
       5  (22E+) Select 486 Processor Interface. If bit 4 set, this bit is set
           for 486 Local bus systems with 1x clocking, clear for 386 Local Bus
           systems with 2x clocking
          (32 only) Disable All Reads. If set all register reads are ignored,
           except for port 94h, 102h, 3C3h and 46E8h
       6  (22E+) Enable 16bit BIOS if set
          (32 only) VSE Disable. If set accesses to the VSE register (46E8h
           or 3C3h) are ignored
       7  (22E+) Enable BIOS Zero Wait State. If set the ZWS signal is
           asserted during accesses to C0000h-C7FFFh, resulting in zero wait
           states
          (32 only) VSE Read Disable. If set the VSE register (46E8h or 3C3h)
           is write only

3C4h index 23h (R/W):  Performance Select Register
bit    0  (not 32) Video Memory Width Select. Set if the video memory is 32
           bit wide, clear if it is 16bit wide.
       1  (not 32) Selects 3 clock RAS cycles if set. Should not be set!!
       2  (not 22E+,32) Enables Fast Page Mode if set. Set by external
           resistor.
          (32 only) 4 Clock RAS# Precharge. If set the RAS precharge time is 4
           clocks, 3 if clear.
       3  (22E+,32) Select AT or PS/2 Style BIOS. If clear AT style operation
           is selected and mode switches between monochrome and color modes
           require the BIOS equipment flag to be updated, if clear PS/2 mode
           operation is selected and mode switches are unrestricted.
       4  (22E,22E+) Wait State Select. In ATbus systems zero wait states is
           enabled if clear. In Local Bus mode one wait state if clear, no
           wait states if set
          (32 only) Zero Wait State Select. If set RDY will be asserted in the
           first T2 of a write operation (assuming the write FIFO is not full)
           and RDY will be asserted in the second T2 cycle of a read operation
           assuming the data is not ready
       5  (22E+ only) RAS/CAS Swap. If set the RAS and CAS lines are swapped.
          Allows higher performance on Local Bus systems.
       6  (not 22E+,32) Unlatched Memory Writes (Only in 256 color modes with
          OSC3). If set limits the duration of CHRDY assertion time by
          limiting FIFO fill lengths.
       7  Latched Memory Reads. If set the assertion of CHRDY can be
          eliminated during read cycles.

3C4h index 24h (R/W):  Color Expanded Write Foreground Register.
bit  0-7  When in expanded write mode (3C4h index 26h bit 0 set) a monochrome
          bitmap can be expanded to 256 or 16 colors 8 or 16 pixels at a time.
          '1' bits in the bitmap are expanded to this color. For 16 color
          modes only bit 0-3 are used.

3C4h index 25h (R/W):  Color Expanded Write Background Register.
bit  0-7  When in expanded write mode (3C4h index 26h bit 0 set) a monochrome
          bitmap can be expanded to 256 or 16 colors 8 or 16 pixels at a time.
          '0' bits in the bitmap are expanded to this color. For 16 color
          modes only bit 0-3 are used.

3C4h index 26h (R/W):  Extended Read/Write Control Register.
bit    0  FG/BG Color Expansion Enable. When set enables expansion from
          monochrome bitmaps to full color using 3C4h index 24h and 25h as
          fore- and background colors.
       1  256Color Expansion Enable Mode 1. If set enables 256 color
          expansion. If clear 8bit pixel values can be written to the
          framebuffer as in standard mode 13h. If clear and bit 0 is set then
          16 color expansion is enabled. If set the upper 4 bits of the host
          data will be expanded to four separate pixels, each is the
          foreground color (index 24h) if the corresponding bit is set, the
          background color (index 25h) if it is clear
       2  (not 22E+,32 ?) Color Expansion Enable Mode 2. If set accesses to
           even addresses will work on the upper 4 bits of the data at the
           even address and the lower 4 bits of the data at the following odd
           address. This mode should only be used when the chip is configured
           as a 16 bit device and only with even addresses.
       3  Planar to Packed Pixel Conversion Enable. Enables 16/256 color pixel
          expansion when set. This bit should always be set when bit 1 is.
       4  Packed Pixel Mask Enable. When in packed pixel modes, this bit is
          set to enable pixel masking operations. This bit should be set when
          bit 1 is set.
       5  Packed Pixel Color Compare. When set configures the color compare
          logic to operate on packed pixel data. This bit should be set when
          bit 1 is set.
       6  Quad Word Read Latch for Writes. If set 64 bits are written when 16
          bit latched write operations occurs in write mode 1. Allows fast
          copy of data within the framebuffer.
       7  (22,22E) Address Toggle. When bit 6 is set this bit specifies
            how address information is maintained with the latched data.
          (22E+,32) Color Transparency Enable. If set the upper 4 bits of
            rotated CPU data is the Transparency mask

3C4h index 27h (R/W):  Miscellaneous Feature Select Register.
bit    0  Extended Palette addressing enable. If set I/O address bit 15 is
          passed to the RS2 pin of the palette DAC chip, so that I/O address
          03C6h - 03C9h address the first 4 registers of the DAC chip and
          83C6h - 83C9h address four other registers.
          Useful for advanced DACs with overlay and command registers.
       1  64K/256Kx16 Dual WE DRAMs. If set the 77C22E outputs DRAM interface
          signals for direct interfacing with 64K x 16 DRAMs (22E+:
          64K/256Kx16).
       2  Disable ROM BIOS CS. If set this bit disables the address decoding
          for the BIOS ROM at C000h-C7FFFh thus allowing this area to be used
          for  other adapters.
       3  User Defined Output (I/O Control pin 2). This bit is output on pin 2
          On the 32BLT this is output on pin 126
       4  (22E+,32) IRQ Drive Low. If set (or in MCA mode) the IRQ signal will
           drive low and release, if clear and in AT or Local Bus mode the IRQ
           signal will drive high and release to tristate.
       5  (22E+) Enable Output of Pixel Data. If set disables tristating of
           pixel data when EVID/ is active
          (32 only) 3C0h-3DFh Full Range Addressing. If set LRDY/ is asserted
           for any I/O access in the range 3C0h-3DFh.
       6  (22E+) Enable Output of PCLK. If set disables tristating of PCLK
           when EVID/ is active
          (32 only) Zero Wait State Read Enable. If set a zero wait read cycle
           results if the data is available from the read caches.
       7  (22E+) Enable Output of BLANK/. If set disables tristating of the
           BLANK/ signal when EVID/ is active, if clear BLANK/ is tristated
           when EVID/ is active
          (32 only) Remapped BIOS Write. If set writes to A0000h-AFFFFh are
           written to the BIOS allowing BIOS RAM updates without disabling
           BIOS shadowing and reallocation of C0000h-C7FFFh

3C4h index 28h (R/W):  Color Key Control                        (22E+,32 only)
bit    0  Enable Color Key if set
       1  Color Key Output Control. If set the Color Key Output signal goes
          active on the rising edge of PCLK, if clear on the falling edge.
     2-3  Color Key Sample Interval. Determines the sample interval of the
          pixel byte stream. The sampling begins with the first byte after
          display has been enabled. 0: Every byte, 1: Every second byte,
            2: Every third byte, 3: Every fourth byte.
     4-5  Video Delay. Controls the delay of the tristate control signal after
          a color match in number of sample intervals to delay assertion of
          the tristate control signal. 0: 0 sample intervals, 1: 1, 2: 2, 3: 3
       6  Disable Tristate Output. If set disables the tristating of PCLK and
          PIX during the color match interval, if clear PCLK and PIX will
          tristate during the color match interval
       7  (32 only) Tristate Delay Mode. If set the tristate delay specified
           in bits 4-5 are in bytes, if clear in pixels.

3C4h index 29h (R/W):  Color Key Match Value                    (22E+,32 only)
bit  0-7  The color the Color Key circuitry looks for. When a match is found
          the Color Key Match signal is asserted

3C4h index 2Ah W(R/W):  Color Key Match Value High                   (32 only)
bit 0-15  Bits 8-23 of the Color Kay Match value in index 29h

3C4h index 2Dh (R/W):  CRC Control                                 (22E+ only)
bit    0  Arm CRC Circuit. If set causes the CRC circuit to operate on video
          data for one frame (VSYNC to VSYNC). For interlaced modes two frames
          are used.
       1  If set forces the CRC value to 1. Must be reset prior to CRC testing
       2  Self Test Enable. If set no external data is used for the CRC
          generation. Intended for testing.

3C4h index 2Eh W(R):  CRC Data                                     (22E+ only)
bit 0-15  The generated CRC value.

3C4h index 30h (R/W):  Memory Mapped Register Control                (32 only)
bit    0  Enable Accelerator Control Menu (ACM). If set the ACM is enabled at
          the address specified in index 31h-33h.
       1  Enable Cursor Register Access. If set the Cursor Position registers
          (3C4h index 0Dh-10h) can be accessed at index 0Ch in the ACM.
       2  Enable Primary/Secondary Offset Register Access. If set the Primary
          and Secondary Offset registers (3C4h index 18h,19h,1Ch and 1Dh) can
          be accessed in the ACM

3C4h index 31h 3(R/W):  ACM Aperture Register 1-3                    (32 only)
bit 0-23  Bits 8-31 of the ACM Aperture address. The lower 8 bits are 0.

3C4h index 3Eh (R/W):  BIOS Utility Register 0                       (32 only)
bit  0-7  Scratch Pad
       0  Set for other HiColor DACs
       1  Set for DACs with fourth read of 3C6h = 44h (MUSIC MU9c9910)
       2  Set for DACs with fourth read of 3C6h = B3h (which ??)
       4  Appears to be the inverse of 3C4h index 22h bit 0

3C4h index 3Fh (R/W):  BIOS Utility Register 1                       (32 only)
bit  0-7  Scratch Pad

3d4h index 30h (R/W):  Extended Horizontal Timings Register.
bit    0  Horizontal Total bit 8. Bit 8 of the Horizontal Total register.
          (3d4h index 0). Bit 9 is in index 32h bit 0.
       1  Horizontal Display Enable End bit 8. Bit 8 of the Horizontal Display
          Enable End register (3d4h index 1). Bit 8 is in index 32h bit 1.
       2  Start Horizontal Blanking bit 8. Bit 8 of the Start Horizontal
          Blanking register (3d4h index 2). Bit 9 is in index 32h bit 2.
       3  Start Horizontal Retrace bit 8. Bit 8 of the Start Horizontal
          Retrace register (3d4 index 4). Bit 9 is in index 32h bit 4
       4  (22E, 22E+,32) Interlace Enable. Enables interlace video for high
           resolution graphics modes. Note in interlaced modes the line
           doubling from index 9 bits 0-4&7 is ignored. Also Line Compare
           should not be used with interlaced modes
       5  (22E+,32) Enable Extended End Bits. If set enables the extended end
           bits (index 32h bits 4-7 and index 33h bits 5-7)
       6  (22E+) CRT Clock Divide by Two. If set the video clock is divided
           by 2.
Note: The extended Function Enable Register (3C4h index 5) bit 0 must be 1 to
      access this register.

3d4h index 31h (R/W):  Extended Start Address Register
bit  0-3  Display Start Address bit 16-19. (bit 0-15 are in 3d4h index Ch and
          Dh).
       4  Bit 8 of Address Row Offset. Bit 8 of the CRTC Offset (3d4h index
          13h).

3d4h index 32h (R/W):  Extended Horizontal Timings Two Register     (22E+, 32)
bit    0  Horizontal Total Bit 9. Bit 9 of the Horizontal Total register (3d4h
          index 0). Bit 8 is in index 30h bit 0
       1  Horizontal Display Enable End bit 9. Bit 9 of the Horizontal Display
          End register (3d4h index 1). Bit 8 is in index 30h bit 1
       2  Horizontal Blank Start bit 9. Bit 9 of the Start Horizontal Blanking
          register (3d4h index 2). Bit 8 is in index 30h bit 2.
       3  Horizontal Retrace Start bit 9. Bit 9 of the Start Horizontal