ncr.txt

比较详尽的VGA端口寄存器的文档

   NCR 77C21
   NCR 77C22
   NCR 77C22E    160pin 4MB, 1280x1024 256 col
   NCR 77C22E+   160pin
   NCR 77C32BLT  208pin BitBLT support


3C4h index  5  (R/W):  Extended Function Enable Register
bit    0  Enables extended registers if set (3C4h index >=8, 3d4h index >=30h)
       1  Reserved (always 0).
       2  If set the Hardware Configuration registers (3C4h index 23h bit 0-3,
          index 27h bit 1, index 1Fh bit 5 and index 1Eh bits 0-1) can be
          modified. On the 77c32BLT this bit causes the memory to wrap at 512K
          when set.
     3-7  Reserved

3C4h index  8  (R):  Version Number Register
bit  0-3  Chip revision
     4-7  Product Code: 0=77C22, 1=77C21, 2=77C22E (bits 0-3 <8) or 77C22E+
           (bits 0-3 >=8), 3=77c32BLT.

3C4h index 0Ah (R/W):  Cursor Color One Register
bit  0-7  Foreground color of the Bit Mapped Cursor.
          Selected if plane 0=0 and plane 1=1.

3C4h index 0Bh (R/W):  Cursor Color Zero Register
bit  0-7  Background color of the Bit Mapped Cursor.
          Selected if plane 0=0 and plane 1=0.

3C4h index 0Ch (R/W):  Cursor Control Register
bit    0  Cursor Enable. When set enables the Bit Mapped cursor.
     1-2  Cursor Height select.
          0=16 lines, 1=32 lines, 2=64 lines and 3=128 lines.
       3  Blink Frequency Select. If set the Bit Mapped Cursor is on for 16
          frames and off for another 16 frames. If clear it is on for 8 frames
          and off for another 8 frames.
       4  Blink Enable. If set the Bit Mapped Cursor blinks.
     5-6  (77c22E+,32 only) Cursor Repeat Count. Number of bytes per pixel the
          cursor passes over: 0: 1byte/pixel, 1: 2b/p, 2: 3b/p, 3: 4b/p
       7  (32 only) Cursor Width Select. If set selects a 64pixel wide cursor,
          32pixel if clear

3C4h index 0Dh (R/W):  Cursor X Location High register
bit  0-2  Bits 8-10 of the horizontal position of the Bitmapped Cursor.
          The lower 8 bits are in 3C4h index 0Eh.
     3-7  Reserved

3C4h index 0Eh (R/W):  Cursor X Location Low register
bit  0-7  Lower 8 bits of the horizontal position of the Bitmapped Cursor.
          The upper 3 bits are in 3C4h index 0Dh.

3C4h index 0Fh (R/W):  Cursor Y Location High register
bit  0-1  (22,22E) Bits 8-9 of the vertical position of the Bitmapped Cursor.
          The lower 8 bits are in 3C4h index 10h.
       2  (22E+,32) Bit 10 of the Cursor Vertical position

3C4h index 10h (R/W):  Cursor Y Location Low register
bit  0-7  Lower 8 bits of the vertical position of the Bitmapped Cursor.
          The upper 2 bits are in 3C4h index 0Fh.

3C4h index 11h (R/W):  Cursor X Index Register.
bit  0-4  (22,22E,22E+) Horizontal location of the Hot Spot from the left of
          the cursor.
     0-5  (32) Bit 5 of the Cursor X Index

3C4h index 12h (R/W):  Cursor Y Index Register.
bit  0-6  Vertical location of the Hot Spot from the top of the cursor.
       7  Reserved.

3C4h index 13h (R/W):  Cursor Storage Register High.
bit  0-7  Bits 8-15 of the address of the cursor bitmap. The lower 8 bits are
          in 3C4h index 14h.

3C4h index 14h (R/W):  Cursor Storage Register Low.
bit  0-7  Bits 0-7 of the address of the cursor bitmap. The upper 8 bits are
          in 3C4h index 13h. Must be an even address
Note: The 22E+ and 32 only documents the lower 4 bits of index 14h and doesn't
      document index 13h ??

3C4h index 15h (R/W):  Cursor Storage Offset Register High.
bit  0-7  Bits 8-15 of the Cursor Storage Offset. The lower 8 bits are in 3C4h
          index 16h.

3C4h index 16h (R/W):  Cursor Storage Offset Register Low.
bit  0-7  Bits 0-7 of the Cursor Storage Offset. The upper 8 bits are in 3C4h
          index 15h. If extended memory is enabled (3C4h index 1Eh bit4 set)
          the Cursor Storage Offset is multiplied with 16 and added to the
          Cursor Storage Address to form a 20 bit address.
Note: The cursor map is stored as a #lines*(32+32bit) bitmap
      The behavior of the cursor in each pixel is defined by the combination
      of the pixels from the two 32bit maps (The first pixel of the cursor is
      stored in the last byte):
       1st   2nd    Description
        0     0     Background color (index 0Bh)
        0     1     Foreground color (index 0Ah)
        1     0     screen data (transparent cursor)
        1     1     Inverted screen data (XOR cursor)
Note: It is possible that for the 77c22e revision 2 the pixel order in the map
      should be reversed.

3C4h index 17h (R/W):  Cursor Pixel Mask Register.
bit  0-7  Each bit set allows the corresponding bit in a pixel to be
          affected by the Bitmapped Cursor.

3C4h index 18h (R/W):  Primary Host Offset Register High.
bit  0-7  Bits 8-15 of the Primary Host Offset.
          The lower 8 bits are in 3C4h index 19h.

3C4h index 19h (R/W):  Primary Host Offset Register Low.
bit  0-7  Bits 0-7 of the Primary Host Offset. The upper 8 bits are in 3C4h
          index 18h. If extended memory is enabled (3C4h index 1Eh bit4 is
          set) all Host addresses are modified by multiplying either the
          Primary or the Secondary Host Offset with 16 and adding the result
          to the Host address.3C4h index 1Eh controls which operations use
          which Host Offset.

3C4h index 1Ah (R/W):  Display Offset Register High.                  (22,22E)
bit  0-7  Bits 8-15 of the Display Offset.
          The lower 8 bits are in 3C4h index 1Bh.

3C4h index 1Ah (R/W):  Linear Address Register 0                     (32 only)
bit  0-1  Aperture Size Select. Selects the size of the linear Aperture
               Size:  Selected by:
           0:   1M    Aperture Location 20-31
           1:   2M    Aperture Location 21-31
           2:   4M    Aperture Location 22-31
     4-7  Aperture Location Bits 20-23. Bits 20-23 of the Address of the
          linear Aperture. Bits 24-31 are in index 1Bh. Depending on the
          Aperture Size (bits 0-1) bits 20-21 of the address may not be used.

3C4h index 1Bh (R/W):  Display Offset Register Low.                   (22,22E)
bit  0-7  Bits 0-7 of the Display Offset. The upper 8 bits are in 3C4h index
          1Ah. If extended memory and Display Offset are enabled (3C4h index
          1Eh bit 4 and 3 are both set) the Display Offset is multiplied with
          16 and added to the normal display address.

3C4h index 1Bh (R/W):  Linear Address Register 1                     (32 only)
bit  0-7  Aperture Location Bits 24-31. The upper 8 bits of the Address of the
          linear Aperture. Bits 20-23 are in index 1Ah

3C4h index 1Ch (R/W):  Secondary Host Offset Register High.
bit  0-7  Bits 8-15 of the Secondary Host Offset. The lower 8 bits are in 3C4h
          index 1Dh.

3C4h index 1Dh (R/W):  Secondary Host Offset Register Low.
bit  0-7  Bits 0-7 of the Secondary Host Offset. The upper 8 bits are in 3C4h
          index 1Ch. 3C4h index 1Eh controls which operations use this
          register

3C4h index 1Eh (R/W):  Extended Memory Enable Register.
bit  0-1  DRAM Address Configuration. These bits can only be modified
          if 3C4h index 5 bit 2 is set.  0: 64Kx, 1: 256Kx, 3: 1Mx
       2  Secondary Offset Enable. If this bit and bit 4 are set all read
          operations are modified by multiplying the Secondary Host Offset by
          16 and adding the result to the host address.
       3  (22,22E only) If this bit and bit 4 are set all display addresses
          are modified by multiplying the Display Offset by 16 and adding the
          result to the normal display address.
       4  Extended Memory Enable. If set extended memory is enabled.
     5-7  (22E+,32 only) Primary/Secondary Read/Write Select.
            0:  Write to Primary, Read from Secondary
            1:  Write to Primary, Read toggles from Secondary to Primary ?
            2:  Primary at A0000h-AFFFFh, Secondary at B0000h-BFFFFh.
                Both Read/Write
            3:  Read and Write to Secondary only
            6:  (22E+ only?) Primary at A0000h-A7FFFh, Secondary at A8000h
                 -AFFFFh. Both Read/Write

3C4h index 1Fh (R/W):  Extended Clocking Mode.
bit  0-3  If bit 4 set this determines the font width:
            0   4 bit wide font
            1   7 bit wide font
            2   8 bit wide font
            3   9 bit wide font
            4  10 bit wide font
            5  11 bit wide font
            6  12 bit wide font
            7  13 bit wide font
            8  14 bit wide font
            9  15 bit wide font
           0Bh 16 bit wide font
       4  If set enables extended font width.
       5  (22E,22E+) Clock Output enable if set.
          (32 only) Clock Select Bit 2
       6  (22E,22E+) Clock Select Bit 2
          (32 only) Clock Select Bit 3
       7  Reserved

3C4h index 20h (R/W):  Extended Video Memory Addressing Register
bit    0  Addition of host address bit 16. If set (and 3CEh index 6 bits 2-3 =
          0) the range A0000h-BFFFFh can be used as one 128K window
       1  Extended chain-4 enable if set.
     2-7  Reserved.

3C4h index 21h (R/W):  Extended Pixel Control Register
bit    0  Enable graphics byte path if set. Set in extended 256color modes
       1  Enable packed/nibble pixel format (2 pixels of 4 bits per byte)
          if set.
       2  (32 only) Packed Nibble to Targa Convert Enable. If set 16bit pixel
           data stored as (Bits 0-3 Red, 4-7 Green, 8-11 Blue) (I.e. NeXT) is
           displayed as (Bits 0-4 Red, 5-9 Green, 10-14 Red) (I.e. Targa).
     4-5  Pixel Depth. The number of bytes per pixel. 0: 1-8 bits/pixel
            (1 byte), 1: 9-16b/p (2 bytes), 2: 17-24b/p (3 bytes).
     2-7  Reserved.

3C4h index 22h (R/W):  Bus Width Feed Back Register.
bit    0  (not 32) Enables 16 bit memory access if set.
       1  (not 32) Enables 16 bit I/O access if set
       2  (22E+) Select AT/MCA/CPU Interface. If bit 4 is clear, this bit is
           set for AT busses and clear for MCA busses. If bit 4 set and bit 5
           clear, this bit is set for 386DX systems, clear for 386SX systems.
          (32) AT/MCA Style Operation. If set the Video Subsystem Enable (VSE)
           register is at 46E8h (AT style), if clear at 3C3h (MCA style).
       3  (22E+) Disable CHRDY High. If set CHRDY is driven low and then
           tri-stated, if clear CHRDY is driver low and upon assertion of
           CHRDY momentarily drives it high and then tri-states it to provide