vgaregs.txt

比较详尽的VGA端口寄存器的文档

              Data Rotate register (3CEh index 3) as a function of the CPU
              data and the latches, then data is rotated as specified by the
              same register.
           1: Mode 1 is used for video to video transfers.
              A read access will load the data latches with the contents of
              the addressed byte of video memory. A write access will write
              the contents of the latches to the addressed byte. Thus a single
              MOVSB instruction can copy all pixels in the source address byte
              to the destination address.
           2: Mode 2 writes a color to all pixels in the addressed byte of
              video memory. Bit 0 of the CPU data is written to plane 0 et
              cetera. Individual bits can be enabled or disabled through the
              Bit Mask register (3CEh index 8).
           3: Mode 3 can be used to fill an area with a color and pattern. The
              CPU data is rotated according to 3CEh index 3 bits 0-2 and anded
              with the Bit Mask Register (3CEh index 8). For each bit in the
              result the corresponding pixel is set to the color in the
              Set/Reset Register (3CEh index 0 bits 0-3) if the bit is set and
              to the contents of the processor latch if the bit is clear.
      3  Read Mode
           0: Data is read from one of 4 bit planes depending on the Read Map
              Select Register (3CEh index 4).
           1: Data returned is a comparison between the 8 pixels occupying the
              read byte and the color in the Color Compare Register (3CEh
              index 2). A bit is set if the color of the corresponding pixel
              matches the register.
      4  Enables Odd/Even mode if set (See 3C4h index 4 bit 2).
      5  Enables CGA style 4 color pixels using even/odd bit pairs if set.
      6  Enables 256 color mode if set.

3CEh index  6  (R/W):  Graphics: Miscellaneous Register
bit   0  Indicates Graphics Mode if set, Alphanumeric mode else.
      1  Enables Odd/Even mode if set.
    2-3  Memory Mapping:
           0: use A000h-BFFFh
           1: use A000h-AFFFh   VGA Graphics modes
           2: use B000h-B7FFh   Monochrome modes
           3: use B800h-BFFFh   CGA modes

3CEh index  7  (R/W):  Graphics: Color Don't Care Register
bit   0  Ignore bit plane 0 in Read mode 1 if clear.
      1  Ignore bit plane 1 in Read mode 1 if clear.
      2  Ignore bit plane 2 in Read mode 1 if clear.
      3  Ignore bit plane 3 in Read mode 1 if clear.

3CEh index  8  (R/W):  Graphics: Bit Mask Register
bit 0-7  Each bit if set enables writing to the corresponding bit of a byte in
         display memory.

3d4h index  0  (R/W):  CRTC: Horizontal Total Register
bit 0-7  Horizontal Total Character Clocks-5

3d4h index  1  (R/W):  CRTC: Horizontal Display End Register
bit 0-7  Number of Character Clocks Displayed -1

3d4h index  2  (R/W):  CRTC: Start Horizontal Blanking Register
bit 0-7  The count at which Horizontal Blanking starts

3d4h index  3  (R/W):  CRTC: End Horizontal Blanking Register
bit 0-4  Horizontal Blanking ends when the last 6 bits of the character
         counter equals this field. Bit 5 is at 3d4h index 5 bit 7.
    5-6  Number of character clocks to delay start of display after Horizontal
         Total has been reached.
      7  Access to Vertical Retrace registers if set. If clear reads to 3d4h
         index 10h and 11h access the Lightpen read back registers ??

3d4h index  4  (R/W):  CRTC: Start Horizontal Retrace Register
bit 0-7  Horizontal Retrace starts when the Character Counter reaches this
         value.

3d4h index  5  (R/W):  CRTC: End Horizontal Retrace Register
bit 0-4  Horizontal Retrace ends when the last 5 bits of the character counter
         equals this value.
    5-6  Number of character clocks to delay start of display after Horizontal
         Retrace.
      7  bit 5 of the End Horizontal Blanking count (See 3d4h index 3 bit 0-4)

3d4h index  6  (R/W):  CRTC: Vertical Total Register
bit 0-7  Lower 8 bits of the Vertical Total. Bit 8 is found in 3d4h index 7
         bit 0. Bit 9 is found in 3d4h index 7 bit 5.
Note: For the VGA this value is the number of scan lines in the display -2.

3d4h index  7  (R/W):  CRTC: Overflow Register
bit   0  Bit 8 of Vertical Total (3d4h index 6)
      1  Bit 8 of Vertical Display End (3d4h index 12h)
      2  Bit 8 of Vertical Retrace Start (3d4h index 10h)
      3  Bit 8 of Start Vertical Blanking (3d4h index 15h)
      4  Bit 8 of Line Compare Register (3d4h index 18h)
      5  Bit 9 of Vertical Total (3d4h index 6)
      6  Bit 9 of Vertical Display End (3d4h index 12h)
      7  Bit 9 of Vertical Retrace Start (3d4h index 10h)

3d4h index  8  (R/W):  CRTC: Preset Row Scan Register
bit 0-4  Number of lines we have scrolled down in the first character row.
         Provides Smooth Vertical Scrolling.
    5-6  Number of bytes to skip at the start of scanline. Provides Smooth
         Horizontal Scrolling together with the Horizontal Panning Register
         (3C0h index 13h).

3d4h index  9  (R/W):  CRTC: Maximum Scan Line Register
bit 0-4  Number of scan lines in a character row -1. In graphics modes this is
         the number of times (-1) the line is displayed before passing on to
         the next line (0: normal, 1: double, 2: triple...).
         This is independent of bit 7, except in CGA modes which seems to
         require this field to be 1 and bit 7 to be set to work.
      5  Bit 9 of Start Vertical Blanking
      6  Bit 9 of Line Compare Register
      7  Doubles each scan line if set. I.e. displays 200 lines on a 400
         display.

3d4h index  Ah (R/W):  CRTC: Cursor Start Register
bit 0-4  First scanline of cursor within character.
      5  Turns Cursor off if set

3d4h index  Bh (R/W):  CRTC: Cursor End Register
bit 0-4  Last scanline of cursor within character
    5-6  Delay of cursor data in character clocks.

3d4h index  Ch (R/W):  CRTC: Start Address High Register
bit 0-7  Upper 8 bits of the start address of the display buffer

3d4h index  Dh (R/W):  CRTC: Start Address Low Register
bit 0-7  Lower 8 bits of the start address of the display buffer

3d4h index  Eh (R/W):  CRTC: Cursor Location High Register
bit 0-7  Upper 8 bits of the address of the cursor

3d4h index  Fh (R/W):  CRTC: Cursor Location Low Register
bit 0-7  Lower 8 bits of the address of the cursor

3d4h index 10h (R/W):  CRTC: Vertical Retrace Start Register
bit 0-7  Lower 8 bits of Vertical Retrace Start. Vertical Retrace starts when
         the line counter reaches this value. Bit 8 is found in 3d4h index 7
         bit 2. Bit 9 is found in 3d4h index 7 bit 7.

3d4h index 11h (R/W):  CRTC: Vertical Retrace End Register
bit 0-3  Vertical Retrace ends when the last 4 bits of the line counter equals
         this value.
      4  if clear Clears pending Vertical Interrupts.
      5  Vertical Interrupts (IRQ 2) disabled if set. Can usually be left
         disabled, but some systems (including PS/2) require it to be enabled.
      6  If set selects 5 refresh cycles per scanline rather than 3.
      7  Disables writing to registers 0-7 if set 3d4h index 7 bit 4 is not
         affected by this bit.

3d4h index 12h (R/W):  CRTC: Vertical Display End Register
bit 0-7  Lower 8 bits of Vertical Display End. The display ends when the line
         counter reaches this value. Bit 8 is found in 3d4h index 7 bit 1.
         Bit 9 is found in 3d4h index 7 bit 6.

3d4h index 13h (R/W):  CRTC: Offset register
bit 0-7  Number of bytes in a scanline / K. Where K is 2 for byte mode, 4 for
         word mode and 8 for Double Word mode.

3d4h index 14h (R/W):  CRTC: Underline Location Register
bit 0-4  Position of underline within Character cell.
      5  If set memory address is only changed every fourth character clock.
      6  Double Word mode addressing if set

3d4h index 15h (R/W):  CRTC: Start Vertical Blank Register
bit 0-7  Lower 8 bits of Vertical Blank Start. Vertical blanking starts when
         the line counter reaches this value. Bit 8 is found in 3d4h index 7
         bit 3.

3d4h index 16h (R/W):  CRTC: End Vertical Blank Register
bit 0-6  Vertical blanking stops when the lower 7 bits of the line counter
         equals this field. Some SVGA chips uses all 8 bits!

3d4h index 17h (R/W):  CRTC: Mode Control Register
bit   0  If clear use CGA compatible memory addressing system
         by substituting character row scan counter bit 0 for address bit 13,
         thus creating 2 banks for even and odd scan lines.
      1  If clear use Hercules compatible memory addressing system by
         substituting character row scan counter bit 1 for address bit 14,
         thus creating 4 banks.
      2  If set increase scan line counter only every second line.
      3  If set increase memory address counter only every other character
         clock.
      5  When in Word Mode bit 15 is rotated to bit 0 if this bit is set else
         bit 13 is rotated into bit 0.
      6  If clear system is in word mode. Addresses are rotated 1 position up
         bringing either bit 13 or 15 into bit 0.
      7  Clearing this bit will reset the display system until the bit is set
         again.

3d4h index 18h (R/W):  CRTC: Line Compare Register
bit 0-7  Lower 8 bits of the Line Compare. When the Line counter reaches this
         value, the display address wraps to 0. Provides Split Screen
         facilities. Bit 8 is found in 3d4h index 7 bit 4.
         Bit 9 is found in 3d4h index 9 bit 6.

3d4h index 22h (R):  Memory Latch Register                       (VGA - Undoc)
bit 0-7  Reads the contents of the Graphics Controller Memory Data Latch for
         the plane selected by 3C0h index 4 bit 0-1 (Read Map Select).
Note: This register is not documented by IBM and may not be available on all
      clones.

3d4h index 24h (R):  Attribute Controller Toggle Register.       (VGA - Undoc)
bit 0-4  Attribute Controller Index.
         The current value of the Attribute Index Register.
      5  Palette Address Source. Same as 3C0h bit 5.
      7  If set next read or write to 3C0h will access the data register.
Note: This register is not documented by IBM and may not be available on all
      clones.

3d4h index 30h-3Fh (W):  Clear Vertical Display Enable.          (VGA - Undoc)
bit   0  Setting this bit will clear the Vertical Display Enable thus blanking
         the display for the rest of the frame and giving the CPU total access
         to display memory until the start of the next frame.
Note: This register is not documented by IBM and may not be available on all
      clones.

3dAh (R):  Input Status #1 Register
bit   0  Either Vertical or Horizontal Retrace active if set
      3  Vertical Retrace in progress if set

3dAh (W):  Feature Control Register
bit   3  Vertical Sync Select. If set Vertical Sync to the monitor is the
         logical OR of the vertical sync and the vertical display enable.
Note: This register can be read from port 3CAh.