vgaregs.txt

比较详尽的VGA端口寄存器的文档

3C0h:  Attribute Controller: Address register
bit 0-4  Address of data register to write to port 3C0h or read from port 3C1h
      5  If set screen output is enabled and the palette can not be modified,
         if clear screen output is disabled and the palette can be modified.


Port 3C0h is special in that it is both address and data-write register.
An internal flip-flop remembers whether it is currently acting as address or
 data register. Data reads happen from port 3C1h.
Accesses to the attribute controller must be separated by at least 250ns.
Reading port 3dAh will reset the flip-flop to address mode.


3C0h index 0-Fh  (R/W):  Attribute: Palette
bit 0-5  Index into the 256 color DAC table. May be modified by 3C0h index
          10h and 14h.

3C0h index 10h (R/W):  Attribute: Mode Control Register
bit   0  Graphics mode if set, Alphanumeric mode else.
      1  Monochrome mode if set, color mode else.
      2  9-bit wide characters if set.
         The 9th bit of characters C0h-DFh will be the same as
         the 8th bit. Otherwise it will be the background color.
      3  If set Attribute bit 7 is blinking, else high intensity.
      5  If set the PEL panning register (3C0h index 13h) is temporarily set
         to 0 from when the line compare causes a wrap around until the next
         vertical retrace when the register is automatically reloaded with
         the old value, else the PEL panning register ignores line compares.
      6  If set pixels are 8 bits wide. Used in 256 color modes.
      7  If set bit 4-5 of the index into the DAC table are taken from port
         3C0h index 14h bit 0-1, else the bits in the palette register are
         used.

3C0h index 11h (R/W):  Attribute: Overscan Color Register.
bit 0-5  Color of screen border. Color is defined as in the palette registers.

3C0h index 12h (R/W):  Attribute: Color Plane Enable Register
bit   0  Bit plane 0 is enabled if set.
      1  Bit plane 1 is enabled if set.
      2  Bit plane 2 is enabled if set.
      3  Bit plane 3 is enabled if set.
    4-5  Video Status MUX. Diagnostics use only.
         Two attribute bits appear on bits 4 and 5 of the Input Status
         Register 1 (3dAh). 0: Bit 2/0, 1: Bit 5/4, 2: bit 3/1, 3: bit 7/6

3C0h index 13h (R/W):  Attribute: Horizontal PEL Panning Register
bit 0-3  Indicates number of pixels to shift the display left
         Value  9bit textmode   256color mode   Other modes
           0          1               0              0
           1          2              n/a             1
           2          3               1              2
           3          4              n/a             3
           4          5               2              4
           5          6              n/a             5
           6          7               3              6
           7          8              n/a             7
           8          0              n/a            n/a

3C0h index 14h (R/W):  Attribute: Color Select Register
bit 0-1  If 3C0h index 10h bit 7 is set these 2 bits are used as bits 4-5 of
         the index into the DAC table.
    2-3  These 2 bits are used as bit 6-7 of the index into the DAC table
         except in 256 color mode.
Note: this register does not affect 256 color modes.

3C2h (R):  Input Status #0 Register
bit   4  Status of the switch selected by the Miscellaneous Output
         Register 3C2h bit 2-3. Switch high if set.
      7  (EGA Only ??) If set IRQ 2 has happened due to Vertical Retrace.
         Should be cleared by IRQ 2 interrupt routine by clearing port 3d4h
         index 11h bit 4.

3C2h (W):  Miscellaneous Output Register
bit   0  If set Color Emulation. Base Address=3Dxh else Mono Emulation. Base
         Address=3Bxh.
      1  Enable CPU Access to video memory if set
    2-3  Clock Select. 0: 25MHz, 1: 28MHz
      5  When in Odd/Even modes Select High 64k bank if set
      6  Horizontal Sync Polarity. Negative if set
      7  Vertical Sync Polarity. Negative if set
         Bit 6-7 indicates the number of lines on the display:
            1:  400, 2: 350, 3: 480
Note: Set to all zero on a hardware reset.
Note: This register can be read from port 3CCh.

3C3h (W):  Video Subsystem Enable Register
bit   0  Enables the VGA display if set

3C4h index  0  (R/W):  Sequencer: Reset
bit   0  Synchronous Reset just as bit 1
      1  Synchronous Reset if clear

3C4h index  1  (R/W):  Sequencer: Clocking Mode
bit   0  If set character clocks are 8 dots wide, else 9.
      2  If set loads video serializers every other character
         clock cycle, else every one.
      3  If set the Dot Clock is Master Clock/2, else same as Master Clock
          (See 3C2h bit 2-3). (Doubles pixels). Note: on some SVGA chipsets
         this bit also affects the Sequencer mode.
      4  If set loads video serializers every fourth character clock cycle,
         else every one.
      5  if set turns off screen and gives all memory cycles to the CPU
         interface.

3C4h index  2  (R/W):  Sequencer: Map Mask Register
bit   0  Enable writes to plane 0 if set
      1  Enable writes to plane 1 if set
      2  Enable writes to plane 2 if set
      3  Enable writes to plane 3 if set

3C4h index  3  (R/W):  Sequencer: Character Map Select Register
bit 0,1,4  Selects VGA Character Map (0..7) if bit 3 of the character
           attribute is clear.
    2,3,5  Selects VGA Character Map (0..7) if bit 3 of the character
           attribute is set.
Note: Character Maps are placed as follows:
      Map 0 at 0k, 1 at 16k, 2 at 32k, 3: 48k, 4: 8k, 5: 24k, 6: 40k, 7: 56k

3C4h index  4  (R/W):  Sequencer: Memory Mode Register
bit   0  Set if in an alphanumeric mode, clear in graphics modes.
      1  Set if more than 64kbytes on the adapter.
      2  Enables Odd/Even addressing mode if set. Odd/Even mode places all odd
         bytes in plane 1&3, and all even bytes in plane 0&2.
      3  If set address bit 0-1 selects video memory planes (256 color mode),
         rather than the Map Mask and Read Map Select Registers.

3C4h index 7 (R/W):  Sequencer Horizontal Character Counter Reset Register.
Note: Undocumented by IBM. May not be available in all clones.
      A write to this register will cause the Horizontal Character Counter
      to be held reset (=0) until a write happens to any of the Sequencer
      registers index 0..6.
      The Vertical Line counter is clocked by a signal derived from the
      Horizontal Display Enable (which does not occur if the Horizontal
      Character Counter is held reset).
      Thus a write to index 7 during Vertical Retrace can stop the display
      timing and allow software to start the next frame reasonably
      synchronous to an external event.

3C6h (R/W):  PEL Mask
bit 0-7  This register is anded with the palette index sent for each dot.
         Should be set to FFh.

3C7h (R):  DAC State Register
bit 0-1  0 indicates the DAC is in Write Mode and 3 indicates Read mode.

3C7h (W):  PEL Address Read Mode
bit 0-7  The PEL data register (0..255) to be read from 3C9h.
Note: After reading the 3 bytes at 3C9h this register will increment,
      pointing to the next data register.

3C8h (R/W):  PEL Address Write Mode
bit 0-7  The PEL data register (0..255) to be written to 3C9h.
Note: After writing the 3 bytes at 3C9h this register will increment, pointing
      to the next data register.

3C9h (R/W):  PEL Data Register
bit 0-5  Color value
Note:  Each read or write of this register will cycle through first the
       registers for Red, Blue and Green, then increment the appropriate
       address register, thus the entire palette can be loaded by writing 0 to
       the PEL Address Write Mode register 3C8h and then writing all 768 bytes
       of the palette to this register.

3CAh (R):  Feature Control Register
Bit   3  Vertical Sync Select. If set Vertical Sync to the monitor is the
         logical OR of the vertical sync and the vertical display enable.
Note: This register is written to port 3dAh and read from 3CAh.

3CCh (R):  Miscellaneous Output Register
bit   0  If set Color Emulation. Base Address=3Dxh else Mono Emulation. Base
         Address=3Bxh.
      1  Enable CPU Access to video memory if set
    2-3  Clock Select. 0= 25MHz, 1= 28MHz, 2= Reserved
      5  When in Odd/Even modes Select High 64k bank if set
      6  Horizontal Sync Polarity. Negative if set
      7  Vertical Sync Polarity. Negative if set
         Bit 6-7 indicates the number of lines on the display:
            0=Reserved, 1=400, 2=350, 3=480.
Note: This register is written to port 3C2h and read from port 3CCh.

3CEh index  0  (R/W):  Graphics: Set/Reset Register
bit   0  If in Write Mode 0 and bit 0 of 3CEh index 1 is set a write to
         display memory will set all the bits in plane 0 of the byte to this
         bit, if the corresponding bit is set in the Map Mask Register (3CEh
         index 8).
      1  Same for plane 1 and bit 1 of 3CEh index 1.
      2  Same for plane 2 and bit 2 of 3CEh index 1.
      3  Same for plane 3 and bit 3 of 3CEh index 1.

3CEh index  1  (R/W):  Graphics: Enable Set/Reset Register
bit   0  If set enables Set/reset of plane 0 in Write Mode 0.
      1  Same for plane 1.
      2  Same for plane 2.
      3  Same for plane 3.

3CEh index  2  (R/W):  Graphics: Color Compare Register
bit 0-3  In Read Mode 1 each pixel at the address of the byte read is compared
         to this color and the corresponding bit in the output set to 1 if
         they match, 0 if not. The Color Don't Care Register (3CEh index 7)
         can exclude bitplanes from the comparison.

3CEh index  3  (R/W):  Graphics: Data Rotate
bit 0-2  Number of positions to rotate data right before it is written to
         display memory. Only active in Write Mode 0.
    3-4  In Write Mode 2 this field controls the relation between the data
         written from the CPU, the data latched from the previous read and the
         data written to display memory:
           0: CPU Data is written unmodified
           1: CPU data is ANDed with the latched data
           2: CPU data is ORed  with the latch data.
           3: CPU data is XORed with the latched data.

3CEh index  4  (R/W):  Graphics: Read Map Select Register
bit 0-1  Number of the plane Read Mode 0 will read from.

3CEh index  5  (R/W):  Graphics: Mode Register
bit 0-1  Write Mode: Controls how data from the CPU is transformed before
         being written to display memory:
           0: Mode 0 works as a Read-Modify-Write operation.
              First a read access loads the data latches of the VGA with the
              value in video memory at the addressed location. Then a write
              access will provide the destination address and the CPU data
              byte. The data written is modified by the function code in the