chips.txt

比较详尽的VGA端口寄存器的文档

  Chips and Technologies Super VGA Chip Sets:


    82c450    1M VRAM    A '453 with VRAM
    82c451  256k DRAM    max 800x600 16col
    82c452    1M DRAM    max 640x480 256col, 1024x768 16col
    82c453    1M DRAM    max 800x600 256 col
    82c455  256k DRAM    Flat Panel version
    82c456  256k DRAM    do
    82c457               do. Full color.
    F65520   1M  D/VRAM  do. Full color. max 1280x1024 16c & 800x600 256 col
    F65530   1M  D/VRAM  do. Full color. max 1280x1024 16c & 800x600 256 col
                         Supports Local Bus.
    F65510    LCD/CRT controller
    F65525    LCD/CRT controller
    F65535    LCD/CRT controller
    F65540     do
    F65545     do


Wingine series:
    64200   2M           Linear frame buffer
    64300   2M
    64310


 94h (R/W):  Setup Control Register for Microchannel boards
bit 0-2  Reserved
      3  Enables Adapter VGA if set
      4  Enters Setup Mode if set
    5-7  Reserved
Note: This is the same register as 46E8h.

100h (R):  Microchannel ID low
bit 0-7  Bit 0-7 of Microchannel Card ID

101h (R):  Microchannel ID high
bit 0-7  Bit 8-15 of Microchannel Card ID

102h (R/W):  Global Enable
bit   0  VGA is enabled if set.

103h (R/W):  Multiple Enable
bit 0-3  Multiple VGA Enable
      4  Must be 0 for proper operation of 82c455/6/7.
      6  Extension registers at 3B6h/7h if set, 3D6h/7h if not.
      7  Extension Registers Access Enable. VGA Extension registers at 3d7h
         can only be accessed if this bit is set.
Note: This register only available in Setup Mode.

104h (R):  Global ID (Setup)                                       (not 655xx)
bit 0-7  Chip I/D.  0A5h if Chips and Tech Chip set.
Note: this register can only be read if the chip is in setup mode (46E8h/94h
      bit 4 is set)

3C3h (R/W):  Setup Control PS/2
bit   0  Enables motherboard VGA if set
      4  Enters Setup mode if set

3CAh (R):  Feature Control Register                                 (82c45x ?)
bit 0-1  If 3C2h/3CCh bits 2-3 is 2, this field selects one of 4 clocks
Note: This is an extension of a standard VGA register, see VGA.TXT for
      other fields in this register. This register can be written at 3DAh

3d4h index 22h (R/W):  CPU Data Latch or Color Compare from last read

3d4h index 24h (R/W):  Attribute Controller flip/flop

3d6h index  0  (R):  Chip Version
bit 0-2  Revision number
      3  Reserved for 450-457,64200,65510-65535, extra chipcode bit
          for the CT64300,64310, 65540,65545
    4-7  Chipcode:
          0: 451  1:452  2:455  3:453  4: 450, 5:456  6:457
          7: 65520, 8:65530, 9: 65510, 0Ah: 64200, 0Ch: CT65535
          0Bh: CT64300 (bit 3 clear), CT64310 (bit 3 set)
          0Dh: CT65540 (bit 3 clear), CT65545 (bit 3 set)

3d6h index  1  (R):  DIP Switch Register
bit 0-6  State of the DIP switches.
    0-7  (655x0) Read from Memory Address bus A on Reset.
         Bit 0-1: CPU Bus type
                   0=PI bus, 1=MC bus, 2=Local bus (65530 only), 3=ISA bus.
               2: Pixel Clock Source (OSC/)
                   0: CLK0-CLK3 are pixel clock inputs.
                      CLK0 or CLK1 is MCLK input.
                   1: CLK0 is MCLK input.
                      CLK1 is pixel clock input.
                      CLK2 is CLKSEL0 output.
                      CLK3 is CLKSEL1 output.
               3: Memory Clock Source (56M/)
                    0: MCLK = 56.644 MHz (80ns RAM)
                       If bit 2 is 0:
                         CLK0 is 50.350 MHz
                         CLK1 is 56.644 MHz (MCLK source)
                         CLK2 is 40.000 MHz
                         CLK3 is 44.900 MHz
                       If bit 2 is 1:
                         MCLK (CLK0) is 56.644 MHz
                         Clock Select 0 is 40.000 MHz
                         Clock Select 1 is 50.350 MHz
                         Clock Select 2 is user defined
                         Clock Select 3 is 44.900 MHz
                    1: MCLK = 50.350 MHz (100ns RAM)
                       If bit 2 is 0:
                         CLK0 is 50.350 MHz
                         CLK1 is 28.322 MHz (MCLK source)
                         CLK2 is 40.000 MHz
                         CLK3 is 44.900 MHz
                       If bit 2 is 1:
                         MCLK (CLK0) is 50.350 MHz
                         Clock Select 0 is 40.000 MHz
                         Clock Select 1 is 28.322 MHz
                         Clock Select 2 is user defined
                         Clock Select 3 is 44.900 MHz
               4: Transceiver Control
                  If set there are no external transceivers (pin 69 is
                  VGARD output), if clear there are external transceivers
                  (pin 69 is ENAVEE/ output).

3d6h index  2  (R/W):  CPU Interface
bit   0  Access to video memory is 16bit if set, 8bit if clear
      1  (82c450-453) I/O access is 16 bit if set, 8bit if clear
         (82c453,0 Only) Fast Font Enable   ???
            The byte written to memory is used as a mask
            for painting foreground color to the pixels
            with the corresponding bit set and background
            color to the rest.
         (655x0 Only) Digital Monitor Clock Mode
            0: CLK0 = 25 MHz, CLK1 = 28 MHz
            1: CLK0 = 14 MHz (56MHz /4 or 28MHz /2)
               CLK1 = 16 MHz (50MHz /3)
      2  (82c450-3,5) Fast MCA buscycle decoding if set
    3-4  (82c450,3 and 455-457) Attribute port pairing
            0: Normal Attribute addressing
            1: 3C1h is both read and write, 8 and 16 bit.
            2: 3C1h is both read and write, 8 bit only.
      5  (Not 82c451/2) 10 bit I/O decoding if set, 16 bit else
      6  (82c450,3 Only) Pel Panning Control
         (655x0 Only) If set external palette registers can be addressed
             at 83C6h-83C9h, Ie A15 is connected to RS2 on the DAC.
      7  (R) Attribute flip-flop status. If set the Attribute register (3C0h)
             is currently in Data mode.

3d6h index  3  (R/W):  ROM Interface                               (not 655x0)
bit   0  Disable on-card ROM if set.
         Enable ROM at C0000h-C7FFFh if clear.

3d6h index  4  (R/W):  Memory Mapping
bit 0-1  (82c452/3/) Display Memory Size:  0: 256Kb, 1: 512Kb, 2: 1Mb.
         (655xx) Memory Configuration
                  0: 2 x 256Kx4 D/VRAM  256K tot   8 bit datapath
                     (6554x) 1Mb ??
                  1: 4 x 256Kx4 D/VRAM  512K tot  16 bit datapath
                  2: (6554x) 1Mb
                  3: 2 x 512Kx8   DRAM    1M tot  16 bit datapath
         (643xx) Display Memory Size:  0: 256Kb, 1: 512Kb,
                  2: 1Mb/2Mb (depending on index Fh bits 0-1).
      2  (82c451/5/6/7) Enable bank access if set
         (82c452/3, 655x0) If set CRTC Address can cross bank boundaries.
      3  (82c457) If set DRAM timing is for 64Kx16 (4 WE, 1 CAS)
                  if clear for 64Kx4 (4 CAS, 1 WE).
         (655x0)  Enables bank addressing if set.
      4  (655x0)  If set VRAM interface, else DRAM interface.
      5  (655x0)  If set CPU memory write buffer is enabled.
      6  (655x0)  If set enables 0WS capability.
      7  (655x0)  If set allows faster 0WS cycle timing.

3d6h index  5h (R/W):  Sequencer Control                        (452/3/7 only)
bit   2  (82c457)  Clock Pin Polarity.
                   If set CLK0 is defined as a common clock and CLK1/S0
                   and CLK2/S1 are select outputs. If clear one of CLK0,
                   CLK1 and CLK2 is selected as the display clock.

3d6h index  6h (R/W):  DRAM Interface                            (82c452 only)

3d6h index  6h (R/W):  Palette Control Register             (64300,655x0 only)
bit   0  If set enables external DAC if 3d6h index 6 bit 0 is 0.
      1  If set disables the internal DAC.
         Causes the DAC to power down and tri-states the outputs.
      2  (655x0) If set enables 16 bit/pixel operation.
         Timing to an external DAC will be SC11486 (Tseng) compatible.
         (Two bytes output per pixel, one on the rising edge of PCLK
         and one on the falling edge).
      3  (655x0) If set 16 bit pixels are 5 red-6 green-5 blue.
         If clear they are 5 bits of each.
    2-3  (64300) DAC mode. 0: Palette, 1: 15bit, 2: 24bit, 3: 16bit
      4  If set the Sense Status bit (3C2h bit 4) is driven by the SENSE
         pin from external logic.
      5  If set bypasses the internal RAMDAC.
         This bit should always be clear.
    6-7  Color Reduction Select.
         In flat panel modes these bits determine the algorithm used to
         reduce 18 bit color data to 6 bits for mono panels.
          0: NTSC weighting, 1: Equivalent weight, 2: Green only, 3: Color.

3d6h index  8h (R/W):  General Purpose Output Select B Register.
                                                            (451/2/5/6/7 only)
bit   0  Select bit B for ERMIN/ pin.
      1  Select bit B for TRAP/ pin.
      2  (82c457) If set PNL14 pin outputs panel data bit 14,
         if clear PNL14 pin outputs DATEN/.

3d6h index 08h W(R/W):                                           (64300,65535)
bit 0-7  (64300) Low bits of the Linear Frame buffer address ?
   8-15  (64300) Linear Frame buffer address bits 24-31.
   3-14  (65535) Linear Frame Buffer address bits 20-31.
    0-?  (6554x) Linear Frame Buffer address bits 20-

3d6h index  9h (R/W):  General Purpose Output Select A Register.
                                                            (451/2/5/6/7 only)
bit   0  Select bit A for ERMIN/ pin.
      1  Select bit A for TRAP/ pin.
         Select A and B determine the output on the pin:
           B      A        Output
         clear  clear      Normal
         clear   set       3-State
          set   clear      Force low
          set    set       Force high

3d6h index 0Ah (R/W):  Cursor Address Top                      (82c452/3 Only)
bit 0-1  Cursor Address bit 16,17
    2-7  Reserved

3d6h index 0Bh (R/W):  CPU Paging                          (82c451/5/6/7 only)
bit 0-1  Bank number in 64k chunks.
Note: This Bank register is used if in a 256 color mode and the chip is a
      82c451/5/6/7.

3d6h index 0Bh (R/W):  Memory Paging Register           (82c452/3, 655x0 only)
bit   0  Enable extended paging (256 color paging) if set
      1  If set Dual Pages are enabled. A0000h-A7FFFh uses 3d6h
         index 10h, A8000h-AFFFFh uses 3d6h index 11h.
      2  CPU Address divide by 4 (256 color addressing)
      3  (655x0) If set CPU address divide by 2 is enabled.
      4  (65530) If set Memory is mapped as 1MB linear Memory.
    4-5  (64300) Set to 3 to enable Linear Frame buffer, 0 to disable

3d6h index 0Ch (R/W):  Start Address Top          (82c452/3, 64300,655x0 Only)
bit 0-1  (655xx) Display Start Address bit 16-17.
    0-2  (64300) Display Start Address bit 16-18.
      4  (64300) Bit 8 of the Single/Low bank register. Bits 0-7 are in 3d6h
            index 10h

3d6h index 0Dh (R/W):  Auxiliary Offset Register
bit   0  Bit 8 of Offset field. If set each line is >255 words.
      1  Bit 8 of simulated Offset field.
      2  (643xx) CRTC Offset bit 8. Bits 0-7 are in 3d4h index 13h

3d6h index 0Eh (R/W):  Text Mode                          (82c452, 655x0 Only)
bit   0  (82c452) Extended text Mode Control ??
      1  (82c452) Enable anti-aliased fonts if set
      2  (655x0)  If set cursor is non-blinking.
      3  (655x0)  If set Cursor style is Exclusive-Or.

3d6h index 0Fh (R/W):  Software Flags 2                     (643xx,655xx only)
bit 0-7  Software flags.
    0-1  (643xx) Video RAM. 0: 256K, 1: 512K, 2: 1MB, 3: 2MB

3d6h index 10h (R/W):  Single/Low Map                   (82c452/3, 6xxxx Only)
bit 0-5  (82c452) Bank no in 4K/16K chunks.
    0-7  (82c453,64300) Bank no in 1K/4K chunks.
Note: This Bank register is used if in single-paging mode or if addressing the
      lower half (32 or 64Kb) of the adapters address range.

3d6h index 11h (R/W):  High Map                         (82c452/3, 655x0 Only)
bit 0-5  (82c452) Bank no in 4K/16K chunks.
    0-7  (82c453) Bank no in 1K/4K chunks.
Note: This Bank register is used if addressing the upper half (32 or 64Kb) of
      the adapters address range.

3d6h index 14h (R/W):  Emulation Mode Register
bit 0-1  Emulation Mode:
          0=VGA/EGA, 1=CGA, 2=MDA and 3=Hercules.
      2  (R) Hercules Configuration (3BFh) bit 0 Readback.
         If set it is possible to set the Graphics Mode bit (3B8h bit 1).
      3  (R) Hercules Configuration (3BFh) bit 1 Readback.
         If set it is possible to set the Graphics Page bit (3B8h bit 7).
      4  Display Enable Status Mode.
         If set bit 0 of the Input Status Register 1 (3dAh)
         shows the Hsync Status (as MDA/Hercules), if clear the
         Display Enable is shown (as CGA/VGA).
      5  Vertical Retrace Status Mode.
         If set bit 3 of the Input Status Register 1 (3dAh)
         shows the Video signal (as MDA/Hercules), if clear the
         Vertical Retrace status is shown (as CGA/VGA).
      6  Vsync Status Mode.
         If clear bit 7 of the Input Status Register 1 (3dAh)
         shows the Vsync Status (as MDA/Hercules).
      7  Interrupt Output Function.
         If clear the IRQ pin will always 3-state, if set it
         will 3-state only when interrupts are disabled.

3d6h index 15h (R/W):  Write Protect Register.
bit   0  Write Protect Group 1 Registers.
         If set the Sequencer (3C4h), Graphics Controller (3CEh)
         and Attribute Controller (3C0h) registers are write protected.
      1  Write Protect Group 2 Registers.
         If set the Cursor Size Register (3d4h index 9 bits 0-4)
         and the Character Height registers (3d4h index 0Ah and 0Bh)
         are write protected.
      2  Write Protect Group 3 Registers.