targa.txt

比较详尽的VGA端口寄存器的文档

Targa
Targa+

Usually the Targa+ operates in Non-Contigous mode where the 16 I/O registers
used are spread in 4 groups of 4 registers each separated by 400h. By setting
a jumper the Targa+ can operate in Contigous mode where the 16 registers are
laid out sequentially. Also the base I/O address is set by jumpers.

Note that this is one adapter where the indexed registers can really be 16bit
wide, so that the notation W(R/W) indicates ONE 16bit index, not two 8bit ones

        Contiguous:  Non-Contiguous:   Read:       Write:
Reg00:    + 00h        + 0000h        VIDSTAT     COLOR0
Reg01:    + 01h        + 0001h                    COLOR1
Reg02:    + 02h        + 0002h        CTL         COLOR2
Reg03:    + 03h        + 0003h        MASKL       COLOR3
Reg04:    + 04h        + 0400h        LBNK        VIDCON
Reg05:    + 05h        + 0401h        READAD      INDIRECT
Reg06:    + 06h        + 0402h        MODE1       HUESAT
Reg07:    + 07h        + 0403h        OVSTRT      OVSTRT
Reg08:    + 08h        + 0800h        USCAN       MASKL
Reg09:    + 09h        + 0801h        MASKH       MASKH
Reg10:    + 0Ah        + 0802h        OSCAN       LBNK
Reg11:    + 0Bh        + 0803h        HBNK        HBNK
Reg12:    + 0Ch        + 0C00h        ROWC        ROWC
Reg13:    + 0Dh        + 0C01h        MODE2       MODE2
Reg14:    + 0Eh        + 0C02h        RBL         WBL
Reg15:    + 0Fh        + 0C03h        RBH         WBH


Reg00 (R):  VIDSTAT
bit   0  If set an odd field is being displayed if clear an even field.
      1  If clear a sync signal is detected indicating that an external video
         source is connected to the Targa+

Reg00 (W):  COLOR0
bit 0-7  Low byte of the Border Color
Note: this register is also accessible as ADV index E0h

Reg01 (W):  COLOR1
bit 0-7  Second byte of the Border Color
Note: this register is also accessible as ADV index E1h

Reg01 (R):  CTL
bit   0  Set whenever a vertical blanking occurs. Cleared when this register
         is read
    1-3  The version number for the Targa chipset
    4-7  Memory configuration. Ah: T16, Bh: T16P, Eh: T16/32, Fh: T16/32P
          or T64

Reg02 (W):  COLOR2
bit 0-7  Third byte of the Border Color.
         When in 16bit mode this should be set to 0.
Note: this register is also accessible as ADV index E2h

Reg03 (R):  MASKL
This is the read port for Reg08

Reg03 (W):  COLOR3
bit 0-7  High byte of the Border Color.
         When in 16 or 24bit mode this should be set to 0
Note: this register is also accessible as ADV index E3h

Reg04 (R):  LBNK
This is the read port for Reg10

Reg04 (W):  VIDCON
bit   0  LiveMixSrc. 0: Bilevel Blending, 1: Dynamic Blending
    1-5  Contrast. 10h is nominal
      6  Set if inputting from a RGB source, clear for Composite or S-video
         inputs.
Note: This register is also present at Advanced index E4h.

Reg05 (R):  READAD
bit   3  INAE. If set the Targa+ is in Advanced Operating Mode
Note: This is the read port for the ADVANCED register (Std indirect 90h)

Reg05 (W):  INDIRECT
bit 0-7  If the Targa+ is in Advanced Mode (the INAE bit is set) this is the
         index register for the Advanced registers.
         Write the index to this register and read/write the data at Reg14.

Reg06 (R):  MODE1
This is the read port for Reg12

Reg06 (W):  HUESAT
bit 0-4  Hue for input composite video. Nominal 10h
    5-7  Saturation for input composite video. Nominal 4

Reg07 (R/W):  OVSTRT
bit 0-7  Used for standard Targa mode

Reg08 (R):  USCAN
Reading this register places the Targa+ in underscan mode

Reg08 (W):  MASKL
bit 0-7  Low mask byte. Each bit set will protect the corresponding bit(s) in
         memory from change during CPU access. This does not affect capture!
Note: This register can be read from Reg03

Reg09 (R/W):  MASKH
bit 0-7  High mask byte. Each bit set will protect the corresponding bit(s) in
         memory from change during CPU access. This does not affect capture!

Reg10 (R):  OSCAN
Reading this register places the Targa+ in overscan mode

Reg10 (W):  LBNK
bit 0-5  32K bank number for the lower half of the 64K window
Note: This register can be read from Reg04

Reg11 (R/W):  HBNK
bit 0-5  32K bank number for the upper half of the 64K window

Reg12 (R):  ROWCNT
bit 0-7  This register is 0 when the display is in retrace, or else the number
         of the line currently being displayed

Reg12 (W):  MODE1
bit   0  If set the video memory is enabled, if clear the video memory is
         disabled and can not be read or written.
    3-5  In Targa compatibility mode this selects one of eight 64K video
         memory blocks
      6  MOD. If clear the INDIRECT register (reg05) is an index to the
         advanced indirect registers. If set the INDIRECT register is an index
         to the standard indirect registers.
Note: This register can be read from Reg06

Reg13 (R/W):  MODE2
bit 2-3  ZOOM factor. 0: none, 1: x2, 2: x4, 3: x8
    4-5  DISPMODE.
           0: Display from memory with fixed color border
           1: Live video with fixed color border
           2: Overlay mode with live border
           3: Live mode with live border
      6  Enables the capture feature.
      7  GENLOCK. If set the Targa+ will attempt to sync to the clock supplied
         with the incoming video. If clear the Targa+ is in Master Mode and
         provides its own video timing control

Reg14 W(R/W):  RB/WB
bit 0-15  Data port for the Advanced registers. The index is written to Reg05
          and the data is read or written in this register.
          Some of the Advanced registers are 8bits and some 16bits.

ADV index 20h W(R/W):  CLOCK
bit 0-10  The 13.5MHz clock is divided by this value to get the line clock.
          I.e.. 858 gives 13.5MHz/858 = 15.734KHz (NTSC frequency).

ADV index 21h (R/W):  GENCTRL
bit    0  Vertical Preload Mode. If set the vertical counter is reset every
          time the frame alignment is found to be false, if clear the vertical
          counter is reset only after 7 consecutive fields are found to be
          misaligned.
     1-2  Field. Selects the field which is used for frame alignment.
            0: Odd field, 1: Even field, 2: either field is used.
     3-5  (R) If bit 0 is clear, this is the number of consecutive
          misalignments which has happened.

ADV index 40h W(R/W):  VTOTAL
bit 0-10  This is twice the number of lines in a field. If the value is odd,
          interlaced timing will be generated.
   11-15  Should be set to 0

ADV index 41h W(R/W):  HTOTAL
bit  0-8  This is the number of SGCLK pulses in half a scanline
    9-15  Should be set to 0

ADV index 42h W(R/W):  SYNC
bit  0-3  This is twice the number of scanlines used for vertical sync.
     4-7  Should be set to 0
    8-13  This is half the number of SGCLK pulses in one horizontal sync
          pulse.
   14-15  Should be set to 0

ADV index 43h W(R/W):  HPHASE
bit  0-8  When the Targa+ is in Slave Genlock mode, this is the number of
          SGCLK pulses before a Horizontal Reference pulse is generated.
          Depending on bit 9 this is from the start or the middle of the line.
       9  If set the value in bits 0-8 is from the middle of the scanline,
          if clear it is from the beginning of the scanline.
   10-15  Should be set to 0

ADV index 44h W(R/W):  VBEND
bit 0-10  This is twice the number of scanlines blanked for each field.
   11-15  Should be set to 0

ADV index 45h W(R/W):  HBSTRT
bit  0-8  The number of SGCLK pulses from the middle of the scanline to the
          start of the Horizontal Blanking.
       9  Should be set to 1
   10-15  Should be set to 0

ADV index 46h W(R/W):  HBEND
bit  0-8  The number of SGCLK pulses from the end of the scanline to the end
          of Horizontal Blanking.
    9-15  Should be set to 0

ADV index 47h W(R/W):  VSTRT
bit 0-10  This is twice the scanline where display starts. If this value is
          larger than VEND (index 44h) a border is shown in the color defined
          by COLOR0-3 (Reg00-Reg03).
   11-15  Should be set to 0

ADV index 48h W(R/W):  VEND
bit 0-10  This is twice the number of the scanline where display stops.
          If this value is smaller then VTOTAL (index 40h) a border is shown
          in the color defined by COLOR0-3 (Reg00-Reg03).
   11-15  Should be set to 0

ADV index 49h W(R/W):  HSTRT
bit  0-9  The number of SGCLK pulses from the end of the scanline until
          display starts. If this value is larger than HBEND (index 46h) a
          border is shown in the color defined by COLOR0-3 (Reg00-Reg03).
   10-15  Should be 0

ADV index 4Ah W(R/W):  HEND
bit  0-9  The number of SGCLK pulses from the middle of the scanline until the
          display stops. If this value is smaller then HBSTRT (index 45h) a
          border is shown in the color defined by COLOR0-3 (Reg00-Reg03).
   10-15  Should be 0

ADV index 4Bh W(R/W):  BURST
bit  0-6  The number of SGCLK pulses from the start of Horizontal Blanking to
          the start of the color burst signal.
       7  Should be set to 0
    8-13  The width of the color burst in SGCLK pulses.
   14-15  Should be set to 0

ADV index 4Ch W(R/W):  SGCNTRL1
bit  0-3  Delay for sync outputs in number of pixels. Typically 9.
     4-7  Delay for the composite blanking in number of pixels.
          Typically 5.
       8  Should be set to 0
       9  Number of refresh cycles per scan lines
   10-15  Should be set to 0

ADV index 4Dh W(R/W):  SGCNTRL2
bit    0  Should be set to 0
       1  If set use Meander burst mode (PAL), if clear use normal burst mode
          (NTSC).
     2-3  The field generated when doing non-interlaced scanning.
          In normal burst mode (NTSC) 0: Even field, 1: Odd field.
          In Meander burst mode (PAL) 0: field0, 1: field1, 2: field2,
            3: field3
       4  If set the new sync generator is used for access to the new Targa+
          feature set, if clear the original sync generator is used for
          compatibility with the original Targa
       5  If set video display is enabled.
       6  If set video refresh is enabled.
       7  If set enables the sync outputs (Horizontal Sync, Vertical Sync,
          Composite Sync, Composite Blanking, Color Burst and half
          horizontal rate signal used for PAL). If clear these outputs are
          held in their inactive state.
    8-15  Should be set to 0

ADV index 4Eh W(R/W):  SGSTATUS
bit  0-1  The current field being displayed.
          In normal burst mode (NTSC): 0: Even field, 1: Odd field
          In Meander burst mode (PAL):
            0: field0, 1: field1, 2: field2, 3: field3
       2  If set the Targa+ is producing vertical sync.
       3  The vertical drive signal
       4  If set the Targa+ is producing vertical sync.
    5-15  Should be set to 0

ADV index 53h W(R/W):  LINECNT
bit  0-9  The number of the scanline being displayed.
   10-15  Should be set to 0
Note: the lower 8 bits can also be read from the ROWCNT (Reg12) register.