s3.txt

比较详尽的VGA端口寄存器的文档

           all memory banks if set
     3-4  (868/968) Set to 3 to enable "New Memory Mapped I/O"
       4  (801/5) Enable MMIO Access. If set to enables the 32K MMIO (Memory
            Mapped I/O registers) at A0000h-A7FFFh.
          (928 +) Enable MMIO Access. If set the 32K MMIO area at A0000h
            -A7FFFh is used for image transfers via E2E8h and E2EAh, and the
            second 32K MMIO area at A8000h-AFFFFh is used for the command
            registers (82E8h-BEE8h)
       5  (928,964) PAR VRAM. Parallel VRAM Addressing. Parallel if set,
           serial if clear. (964) Only needs to be set when a 64bit pixel bus
           is used (3d4h index 66h bits 4-5 = 2).
          (801/5i) DRAM interleaving if set
       6  SWP NBL. Swap Nibbles. If set swaps the nibbles (4bits) in each byte
          read or written to/from video memory.
       7  (not 864/964) Enable Nibble Write Control if set

3d4h index 54h (R/W):  Extended Memory Control 2 Register              (80x +)
bit  0-2  (not 964) Read Ahead Cache (RAC) Extra Prefetch Control. The number
           of doublewords to prefetch (words/bytes in VGA word/byte mode).
          Only 1,3 and 7 are meaningful.
     3-7  (80x,964) M Parameter.

3d4h index 55h (R/W):  Extended Video DAC Control Register             (80x +)
bit 0-1  DAC Register Select Bits. Passed to the RS2 and RS3 pins on the
         RAMDAC, allowing access to all 8 or 16 registers on advanced RAMDACs.
         If this field is 0, 3d4h index 43h bit 1 is active.
      2  Enable General Input Port Read. If set DAC reads are disabled and the
         STRD strobe for reading the General Input Port is enabled for reading
         while DACRD is active, if clear DAC reads are enabled.
      3  (928) Enable External SID Operation if set. If set video data is
           passed directly from the VRAMs to the DAC rather than through the
           VGA chip
      4  Hardware Cursor MS/X11 Mode. If set the Hardware Cursor is in X11
         mode, if clear in MS-Windows mode
      5  (80x,928) Hardware Cursor External Operation Mode. If set the two
          bits of cursor data ,is output on the HC[0-1] pins for the video DAC
          The SENS pin becomes HC1 and the MID2 pin becomes HC0.
      6  ??
      7  (80x,928) Disable PA Output. If set PA[0-7] and VCLK are tristated.
         (864/964) TOFF VCLK. Tri-State Off VCLK Output. VCLK output tri
          -stated if set

3d4h index 56h (R/W):  External Sync Control 1 Register                (80x +)
bit   0  RMT ON. Remote Mode Operation. If set the VSync pin is the input for
         Gen-Lock
      1  (not 864/964) NTSC Mode. If set enables the special NTSC Horizontal
         counter mode, where two dot clocks are skipped in each scanline,
         relative to the value programmed in the Horizontal Total register
         (3d4h index 0). Typical Horizontal Total value is 114 clocks. Index
          00h = 109.
      2  (not 864/964) PAL Mode.  If set enables the special PAL Horizontal
         counter mode, where one dot clock is skipped in each scanline,
         relative to the value programmed in the Horizontal Total register
         (3d4h index 0). Typical Horizontal Total value is 142 clocks. Index
          00h = 137.
      3  External Sync Mode Select. If Remote Mode is selected (bit 0 is set)
         the falling edge of the VSync input signal resets the Vertical
         counter if this bit is set, or both the Horizontal and Vertical
         counters if this bit is clear.
      4  Preset Frame Select. If bit 0 and 3 are both set, the starting frame
         after the Vertical reset is Odd if this bit is set, even if not.
      5  Disable SYNC Output. If set HSYNC, VSYNC and BLANK are tristated.

3d4h index 57h (R/W):  External Sync Control 2 Register                (80x +)
bit  0-3  Vsync Reset Adjust. The vertical delay of the Vertical counter reset
          from the falling edge of VSync in scan lines. Must be non-zero in
          Remote mode (3d4h index 56h bit 0 set).
     4-7  Hsync Reset Adjust. The horizontal delay of the Horizontal counter
          reset from the falling edge of VSync in character clocks.

3d4h index 58h (R/W):  Linear Address Window Control Register          (80x +)
bit  0-1  Linear Address Window Size. Must be less than or equal to video
          memory size. 0: 64K, 1: 1MB, 2: 2MB, 3: 4MB (928)/8Mb (864/964)
       2  (not 864/964) Enable Read Ahead Cache if set
       3  (80x,928) ISA Latch Address. If set latches address during every ISA
           cycle, unlatches during every ISA cycle if clear.
          (864/964) LAT DEL. Address Latch Delay Control (VL-Bus only). If set
           address latching occours in the T1 cycle, if clear in the T2 cycle
           (I.e. one clock cycle delayed).
       4  ENB LA. Enable Linear Addressing if set.
       5  (not 864/964) Limit Entry Depth for Write-Post. If set limits Write
           -Post Entry Depth to avoid ISA bus timeout due to wait cycle limit.
       6  (928,964) Serial Access Mode (SAM) 256 Words Control. If set SAM
            control is 256 words, if clear 512 words.
       7  (928) RAS 6-MCLK. If set the random read/write cycle time is 6MCLKs,
           if clear 7MCLKs

3d4h index 59h M(R/W):  Linear Address Window Position Register        (80x +)
bit  0-9  (80x,928) Linear Address Window Position.
           This is bit 16-25 of the Linear Address Window Starting Position.
           Bits 26-31 are generated externally and input on the SAUP1 pin.
    0-15  (864/964) Linear Address Window Position.
           This is bit 16-31 of the Linear Address Window Starting Position.
          ISA configurations ignore bits 24-31 of the address (and thus bits
           8-9/15 of this register). If the Linear Address Window Size (3d4h
          index 58h bits 0-1) is >64K the lower 4 (1MB),5 (2MB),6 (4MB) or
           7 (8MB) bits of this register are ignored. For PCI systems bits
          23-31 of the address is common with bits 23-31 of the PCI Base
          Address 0 register at PCI offset 10h. Writes to either register will
          be reflected in the other, but bits 23-31 should be updated through
          the PCI register.

3d4h index 5Bh (R/W):  Extended BIOS Flag 2 Register                   (80x +)
bit  0-7  Scratch Pad.
     0-3  (Diamond) Monitor type. 0: NEC 3Fg, 1: NEC 6Fg, 2: VESA 75Hz,
                     3: NEC 4Fg, 4: Gen90?, 5: CS1024i, NEC 3FGx, 8: Fixed?,
                     9: Sony 1304, 10: Sony 1304s, 11: CS1572, 12: NEC 5FGe,
                     13: Mon100?, 14: Mon120?, 15: Reserved fopr Vmode

3d4h index 5Ch (R/W):  General Output Port Register                    (80x +)
bit  0-3  (R) Clock Select Out. If 3C2h/3CCh bit 2-3 is 3 this is 3d4h index
          42h bits 0-3, else bits 0-1 are 3C2h/3CCh bits 2-3 and bits 2-3 are
          0. Thus this is the resulting clock select signals output.
     4-7  General Output Port. Can be used for external logic.
       4  (ELSA) EEProm Data Bit
       5  (ELSA) EEProm Chip Read Select. Set for read access
          (TVP3025 systems) Connected to RS4 on the TVP3025. Set for Bt485
           mode, clear for TVP3020 mode.
       6  (ELSA) EEProm Clock Bit
       7  (ELSA) EEProm Chip Select. Set to access the EEProm
          (STB Pegasus) Changes Video Memory mapping. If set video memory is
           mapped in the 7C000000h-7FFFFFFFh range (A26-31 = 011111), if clear
           at 0-3FFFFFFh range (A26-31 = 0).

3d4h index 5Dh (R/W):  Extended Horizontal Overflow Register           (80x +)
bit    0  Horizontal Total bit 8. Bit 8 of the Horizontal Total register (3d4h
          index 0)
       1  Horizontal Display End bit 8. Bit 8 of the Horizontal Display End
          register (3d4h index 1)
       2  Start Horizontal Blank bit 8. Bit 8 of the Horizontal Start Blanking
          register (3d4h index 2).
       3  (864,964) EHB+64. End Horizontal Blank +64. If set the /BLANK pulse
           is extended by 64 DCLKs. Note: Is this bit 6 of 3d4h index 3 or
           does it really extend by 64 ?
       4  Start Horizontal Sync Position bit 8. Bit 8 of the Horizontal Start
          Retrace register (3d4h index 4).
       5  (864,964) EHS+32. End Horizontal Sync +32. If set the HSYNC pulse
           is extended by 32 DCLKs. Note: Is this bit 5 of 3d4h index 5 or
           does it really extend by 32 ?
       6  (928,964) Data Transfer Position bit 8. Bit 8 of the Data Transfer
            Position register (3d4h index 3Bh)
       7  (928,964) Bus-Grant Terminate Position bit 8. Bit 8 of the Bus Grant
            Termination register (3d4h index 5Fh).

3d4h index 5Eh (R/W):  Extended Vertical Overflow Register             (80x +)
bit    0  Vertical Total bit 10. Bit 10 of the Vertical Total register (3d4h
          index 6). Bits 8 and 9 are in 3d4h index 7 bit 0 and 5.
       1  Vertical Display End bit 10. Bit 10 of the Vertical Display End
          register (3d4h index 12h). Bits 8 and 9 are in 3d4h index 7 bit 1
          and 6
       2  Start Vertical Blank bit 10. Bit 10 of the Vertical Start Blanking
          register (3d4h index 15h). Bit 8 is in 3d4h index 7 bit 3 and bit 9
          in 3d4h index 9 bit 5
       4  Vertical Retrace Start bit 10. Bit 10 of the Vertical Start Retrace
          register (3d4h index 10h). Bits 8 and 9 are in 3d4h index 7 bit 2
          and 7.
       6  Line Compare Position bit 10. Bit 10 of the Line Compare register
          (3d4h index 18h). Bit 8 is in 3d4h index 7 bit 4 and bit 9 in 3d4h
          index 9 bit 6.

3d4h index 5Fh (R/W):  Bus Grant Termination Position Register       (928,964)
bit  0-7  Bus Grant Termination Position. The termination position in
          character clocks for the BGNT signal. Valid only if 3d4h index 50h
          bit 2 set.

3d4h index 60h (R/W):  Extended Memory Control 3                     (864,964)
bit  0-7  N parameter. Number of 4byte(1Mb) or 8byte(2/4Mb) memory cycles
          reserved for the display FIFO before other requestors are served

3d4h index 61h (R/W):  Extended Memory Control 4                     (864,964)
bit  0-2  L Parameter bits 8-10. Bits 0-7 are in index 62h
       7  ENB DFLC. Enable Display Fetch Length Control (L Parameter) enabled
          if set

3d4h index 62h (R/W):  Extended Memory Control 5                     (864,964)
bit  0-7  L Parameter bits 0-7. Bits 8-10 are in index 61h. Number of bytes
          per scanline divided by 4(for 1Mb - 32bit) or 8(for 2/4Mb - 64bit).
          When the display FIFO has received this many memory cycles the FIFO
          will need no further cycles until the next line starts.

3d4h index 63h (R/W):  Extended Sync Delay Adjust High               (864,964)
bit  0-3  VSYNC Reset Adjust bits 4-7. Bits 0-3 are in 3d4h index 57h bits 0-3
     4-7  HSYNC Reset Adjust bits 4-7. Bits 0-3 are in 3d4h index 57h bits 4-7

3d4h index 64h (R/W):  Genlocking Adjustment Register                (864,964)
bit  0-2  H-Counter Dot Addition Adjust. Adjusts the timing of the H-Counter
          reset delay n Dot Clocks.
       3  H-Counter Dot Addition Adjust enabled if set
     4-6  Character Clock Phase Adjust. Delay (in dot clocks) from the rising
          edge of VSYNC to the character clock.
       7  Character Clock Phase Adjust enabled if set

3d4h index 65h (R/W):  Extended Miscellaneous Control                (864,964)
bit    0  SE DLAY. Delay falling edge of SE. If set the falling edges of SE0-3
          are delayed. This reduces the risc of data contention when several
          memory banks are outputting to the same pixel bus.
       1  DISA 1SC. Disable 1st SC0-1 Output. If set the early SC0-1 output
          during blanking is disabled when split transfers are enabled
       2  ENB 3C3. Enable 3C3h for Video Subsystem Setup. If set 3C3h is used
          for video subsystem setup, if clear 46E8h is used.
     6-7  ADR ADJ. Address adjustment for split transfers. 0: No adjustment
          (32 or 64bit pixel bus), 2: 512word shift register and 128bit pixel
          bus, 3: 256word shift register and 128bit pixel bus.
      When using the TI TVP3020 DAC should be set to: 0: Palette modes
           (4/8bit modes), 1: 15/16bit modes, 2: 32bit modes

3d4h index 66h (R/W):  Extended Miscellaneous Control 1              (864/964)
bit  0-2  DIV-SC. Divide SC,SE and VCLK. 0: SC,SE and VCLK = DCLK, 1: SC,SE
          and VCLK = DCLK/2,  2: SC,SE and VCLK = DCLK/4, 3: SC,SE and VCLK
           = DCLK/8, 4: SC,SE and VCLK = DCLK/16, 5: SC,SE and VCLK = DCLK/32
       3  SC=VCLK. Set SC0 to VCLK Frequency. if set SC = VCLK and SC1 =
          inverted VCLK regardless of bits 4-5.
     4-5  SID-MODE. SID Operation Mode. 0: 64bit serial pixel bus, 1: 32bit
          parallel pixel bus, 2: 128bit serial (or 64bit parallel) pixel bus,
          3: 32bit serial pixel bus.
       6  TOFF PADT. Tri-State Off Pixel Address Bus. If set PA0-7 (the VGA
          pixel bus) is tri-stated.
       7  PCI DE. PCI Bus Disconnect Enabled if set

3d4h index 67h (R/W):  Extended Miscellaneous Control 2         (805i,864/964)
bit    0  VCLK PHS. VCLK Phase With Respect to DCLK. If clear VLKC is inverted
          DCLK, if set VCLK = DCLK.
     1-7  Documented as reserved, however:
     4-7  Pixel format.
             0  Mode  0: 8bit (1 pixel/VCLK)
             1  Mode  8: 8bit (2 pixels/VCLK)
             3  Mode  9: 15bit (1 pixel/VCLK)
             5  Mode 10: 16bit (1 pixel/VCLK)
             7  Mode 11: 24/32bit (2 VCLKs/pixel)
            13  (732/764) 32bit (1 pixel/VCLK)

3d4h index 68h (R/W):  Configuration 3 Register                      (864,964)
bit  0-1  /CAS,/WE,/OE Stretch Time. 0: 4units delay, 1: 3units delay,
            2: 2units delay, 3: 1unit delay
     2-3  MA-D-SEL. Memory Address Depth Select. 1: 128K (512 rows X 256
           coloumns), 3: 256K (512 rows X 512 coloumns).
     4-5  /RAS-LOW. /RAS Low Timing Select. 0: 6.5 MCLKs, 1: 5.5 MCLKs,