s3.txt

比较详尽的VGA端口寄存器的文档

          (ISA Bus) No Wait State. NOWS disabled if clear
          (964) Dual CAS Select. Set for Dual WE, clear for Dual CAS
       4  (ISA bus) Normal MEMCS16 generation if set, external if clear
          (Local Bus) Disable LOCA and SRDY for video DAC accesses if clear
     5-7  Additional Monitor Identification.
            0:  640x480 at 60Hz Non-interlaced (Std VGA)
            1:  640x480 at 70Hz Non-interlaced
            2:  800x600 at 60Hz Non-interlaced
            3:  800x600 at 72Hz Non-interlaced
            4:  800x600 at 56Hz Non-interlaced
            5: 1024x768 at 43Hz Interlaced
            6: 1024x768 at 60Hz Non-interlaced
            7: 1024x768 at 70Hz Non-interlaced
               1280x960 at 46Hz Interlaced
Note: These bits are latched from pins PD[8-15] on reset

3d4h index 38h (R/W):  CR38 Register Lock 1
bit  2-3  Write 2 to unlock. Bit 6-7 must also be set
     6-7  Write 1 to unlock. Bit 3-4 must also be set
Note: Traditionally 48h is used to unlock and 00h to lock

3d4h index 39h (R/W):  CR39 Register Lock 2
bit  0-2  (911/24) Write 5 to unlock the Test Register ?
     5-7  Write 5 to unlock the System Control Registers (3d4h index >=40h)
Note: Traditionally A5h is used to unlock and 5Ah to lock

3d4h index 3Ah (R/W):  CR3A Miscellaneous 1
bit  0-1  Alternate Refresh Count Control. If bit 2 is set this is the number
          of refresh cycles per scanline, rather than 3d4h index 11h bit 6.
       2  Enable Alternate Refresh Count Control (bits 0-1) if set
       3  Top Memory Access (TOP MEM). Forces PCU and CRTC accesses into the
          upper 32k or 64K if set
       4  256 Color Enhanced Mode. Configure Shift registers in the Attribute
          Controller for 8, 16 or 24 bit data if set, 4bit if clear
       5  Enables High Speed Text CPU font writing if set.
       7  (911-928) Enable MEMCS16 Bus Signal. If set MEMCS16 is 16bits, else
            8 bits.
          (964) PCIRB DISA. PCI Read Bursts Disabled if set. 3d4h index 66h
            bit 7 should be set before this bit is set

3d4h index 3Bh (R/W):  CR3B Data Transfer Execute Position Register      (9xx)
bit  0-7  The Horizontal character position of the data transfer execution in
          memory clocks. Usually in the middle of 3d4h index 0 and 3d4h index
          4

3d4h index 3Ch (R/W):  CR3C Interlaced Mode Start/End Register
bit  0-7  Interlace mode frame offset (Typically half the horizontal total).

3d4h index 40h (R/W):  CR40 System Configuration
bit    0  Enable Enhanced Register Access. Enables 8514/a registers
          (x2E8h,x6E8h,xAE8h,xEE8h) if set
       1  (911/24) CPC I/O Select. If set CPC selected VDCRD/WR are I/O
           decoded R/W signals, if clear RAMDAC is selected
          (801/5) Signal Select. If set the MID0 signal is STRD
          (928) Signal Select. If set the MID0 signal becomes STRD if 3d4h
            index 55h bit 2 is set, MID0 becomes BGNT  and MID1 becomes BREQ
            if 3d4h index 55h bit 2 is clear.
       2  (911-928) Write Wait Control (Local Bus only). 1 wait state if set,
           none if clear
       3  (911-928) Enable Fast Write Buffer (FIFO) if set (ISA bus only for
            911/24, all busses for 801/5,928).
       4  (864,964) RDY CTL. Ready Control (VL-bus only). If set there is
           minimum 1 wait state between the assertion of /SADS and /ARDY (for
           command writes), if clear the minimum is 0.
       5  (864,964) WDL DLAY. Write Latching Delay (VL-bus only). If set write
           data is latched on the first rising edge of SCLK after assertion of
           /SRDY, if clear after /RDYIN
     4-5  (911-928) Decode Wait Control (Local Bus only). Number of wait
            states. 0: 0ws, 1: 1ws, 2: 3ws, 3: 2ws
     6-7  (911-928) Read Wait Control.
           Local Bus: Number of wait states  0: 0ws, 1: 1ws, 2: 3ws, 3: 2ws
           ISA Bus (801/5,928): 0 enables the NOWS signal, 1-3 disables
          (864,964) BUS TNO. Bus Turnaround Non-Overlap (VL-bus only).
           Controls the interval between deassertion of /ABEN and the
           assertion of /DBEN (or vice versa).
             0: 1unit, 1: 2units, 2: 3units, 3: 4units

3d4h index 41h (R/W): CR41 BIOS Flag Register
bit  0-4  (Diamond 864/964) Clock index for current mode.
       4  (911/924) Set if we have 1MByte, clear if we have 512KBytes.
       6  Dual Display VGA test size. Set for 32K, clear for 64K
          Note: this might be reversed for 80x/928 ????
       7  Set to enable dual display
Note: Undocumented on the 911

3d4h index 42h (R/W):  CR42 Mode Control
bit  0-3  DCLK Select. These bits are effective when the VGA Clock Select
          (3C2h/3CCh bit 2-3) is 3.
       5  Interlaced Mode if set.

3d4h index 43h (R/W):  CR43 Extended Mode
bit    0  Video Clock Edge Mode Select. If clear video data is output on the
          rising edge of DCLK only, if set on both rising and falling edge.
       1  DAC Register Select bit 2. This bit is output to the palette chip
          RS2 pin, which on advanced DACs works as a 3rd address bit to the
          DAC registers at 3C6h-3C9h.
          (801/5,928) Only active if 3d4h index 55h bits 0-1 is 0
       2  Logical Screen Width bit 8. Bit 8 of the Display Offset Register/
          (3d4h index 13h). (801/5,928) Only active if 3d4h index 51h bits 4-5
          are 0
       3  (911-928) Enable 64K Color Mode. Enables 16bit modes if set
       4  (911-928) Translate Enable. If set the '8514' registers use
          alternate addresses (x148h, x548h, x948h and xD48h), if clear
          standard addresses (x2E8h, x6E8h, xAE8h and xEE8h).
       5  (911/24) Clock Stop Control. If set stops DCK0 (Attribute Control 0)
       6  (911/24) Clock Stop Control. If set stops DCK1 (Attribute Control 1)
       7  (911/24) Clock Stop Control. If set stops GCLK (GE and DM Clock)
          (80x +) Horizontal Counter Double Mode. If set character clocks
            are 16 pixels wide rather than 8.

3d4h index 45h (R/W):  CR45 Hardware Graphics Cursor Mode
bit    0  HWGC ENB. Hardware Graphics Cursor Enable. Set to enable the
          HardWare Cursor in VGA and enhanced modes.
       1  (911/24) Delay Timing for Pattern Data Fetch
       2  (801/5,928) Hardware Cursor Horizontal Stretch 2. If set the cursor
           pixels are stretched horizontally to two bytes and items 0 and 1 of
           the fore/background stacks in 3d4h index 4Ah/4Bh are used.
       3  (801/5,928) Hardware Cursor Horizontal Stretch 3. If set the cursor
           pixels are stretched horizontally to three bytes and items 0,1 and
           2 of the fore/background stacks in 3d4h index 4Ah/4Bh are used.
     2-3  (805i,864/964) HWC-CSEL. Hardware Cursor Color Select.
            0: 4/8bit, 1: 15/16bt, 2: 24bit, 3: 32bit
          Note: So far I've had better luck with: 0: 8/15/16bit, 1: 32bit??
       4  (80x +) Hardware Cursor Right Storage. If set the cursor data is
           stored in the last 256 bytes of 4 1Kyte lines (4bits/pixel) or the
           last 512 bytes of 2 2Kbyte lines (8bits/pixel). Intended for
           1280x1024 modes where there are no free lines at the bottom.
       5  (928) Cursor Control Enable for Brooktree Bt485 DAC. If set and 3d4h
           index 55h bit 5 is set the HC1 output becomes the ODF and the HC0
           output becomes the CDE
          (964) BT485 ODF Selection for Bt485A RAMDAC. If set pin 185 (RS3
           /ODF) is the ODF output to a Bt485A compatible RamDAC (low for even
           fields and high for odd fields), if clear pin185 is the RS3 output.


3d4h index 46h M(R/W):  CR46/7 Hardware Graphics Cursor Origin-X
bit 0-10  The HardWare Cursor X position. For 64k modes this value should be
          twice the actual X co-ordinate.

3d4h index 48h M(R/W):  CR48/9 Hardware Graphics Cursor Origin-Y
bit  0-9  (911/24) The HardWare Cursor Y position.
    0-10  (80x +) The HardWare Cursor Y position.
Note: The position is activated when the high byte of the Y coordinate (index
      48h) is written, so this byte should be written last (not 911/924 ?)

3d4h index 4Ah (R/W):  Hardware Graphics Cursor Foreground Stack       (80x +)
bit  0-7  The Foreground Cursor color. Three bytes (4 for the 864/964) are
          stacked here. When the Cursor Mode register (3d4h index 45h) is read
          the stackpointer is reset. When a byte is written the byte is
          written into the current top of stack and the stackpointer is
          increased. The first byte written (item 0) is allways used, the
          other two(3) only when Hardware Cursor Horizontal Stretch (3d4h
          index 45h bit 2-3) is enabled.

3d4h index 4Bh (R/W):  Hardware Graphics Cursor Background Stack       (80x +)
bit  0-7  The Background Cursor color. Three bytes (4 for the 864/964) are
          stacked here. When the Cursor Mode register (3d4h index 45h) is read
          the stackpointer is reset. When a byte is written the byte is
          written into the current top of stack and the stackpointer is
          increased. The first byte written (item 0) is allways used, the
          other two(3) only when Hardware Cursor Horizontal Stretch (3d4h
          index 45h bit 2-3) is enabled.

3d4h index 4Ch M(R/W):  CR4C/D Hardware Graphics Cursor Storage Start Address
bit  0-9  (911,924) HCS_STADR. Hardware Graphics Cursor Storage Start Address
    0-11  (80x,928) HWGC_STA. Hardware Graphics Cursor Storage Start Address
    0-12  (864,964) HWGC_STA. Hardware Graphics Cursor Storage Start Address
          Address of the HardWare Cursor Map in units of 1024 bytes (256 bytes
          for planar modes). The cursor map is a 64x64 bitmap with 2 bits (A
          and B) per pixel. The map is stored as one word (16 bits) of bit A,
          followed by one word with the corresponding 16 B bits.
          The bits are interpreted as:
             A    B    MS-Windows:         X-11:
             0    0    Background          Screen data
             0    1    Foreground          Screen data
             1    0    Screen data         Background
             1    1    Inverted screen     Foreground
          The Windows/X11 switch is only available for the 80x +.
          (911/24) For 64k color modes the cursor is stored as one byte (8
            bits) of A bits, followed by the 8 B-bits, and each bit in the
            cursor should be doubled to provide a consistent cursor image.
          (801/5,928) For Hi/True color modes use the Horizontal Stretch bits
            (3d4h index 45h bits 2 and 3).

3d4h index 4Eh (R/W):  CR4E HGC Pattern Disp Start X-Pixel Position
bit  0-5  Pattern Display Start X-Pixel Position.

3d4h index 4Fh (R/W):  CR4F HGC Pattern Disp Start Y-Pixel Position
bit  0-5  Pattern Display Start Y-Pixel Position.

3d4h index 50h (R/W):  Extended System Control 1 Register              (80x +)
bit    2  (928,964) Enable BREQ Function. If set the BREQ and BGNT functions
           are enabled.
       3  (not 864/964) Disable LOCA/SRDY. If set disables the LOCA/SRDY
           signals on the Local Bus for writing to the DAC.
     4-5  Pixel Length Select. Selects the pixel length for Enhanced Mode.
           0: 4 or 8 bits/pixel (1 byte), 1: 16 bits/pixel (2 bytes)
           3: 32bits/pixel (4bytes) - 928 and later
     6-7  (80x A&B, 928 rev A-D) Graphics Engine Command Screen Pixel Width.
           0: 1024 or 2048, 1: 640, 2: 800, 3: 1280
   0,6-7  (80x C+,928 E+, 864/964) Graphics Engine Command Screen Pixel Width.
           0: 1024 (or 2048 if 3d4h index 31h bit 1 set) , 1: 1152, 2: 640,
            4: 800 (or 1600 if 4AE8h bit 2 set), 5: 1600, 6: 1280

3d4h index 51h (R/W):  Extended System Control 2 Register              (80x +)
bit    0  (80x) Display Start Address bit 18
     0-1  (928 +) Display Start Address bit 18-19.
          Bits 16-17 are in index 31h bits 4-5, Bits 0-15 are in 3d4h index
          0Ch,0Dh. For the 864/964 see 3d4h index 69h
       2  (80x) CPU BASE. CPU Base Address Bit 18.
     2-3  (928 +) Old CPU Base Address Bits 19-18.
           64K Bank register bits 4-5. Bits 0-3 are in 3d4h index 35h.
           For the 864/964 see 3d4h index 6Ah
     4-5  Logical Screen Width Bit [8-9]. Bits 8-9 of the CRTC Offset register
          (3d4h index 13h). If this field is 0, 3d4h index 43h bit 2 is active
       6  (928,964) DIS SPXF. Disable Split Transfers if set. Spilt Transfers
           allows transferring one half of the VRAM shift register data while
           the other half is being output. For the 964 Split Transfers
           must be enabled in enhanced modes (4AE8h bit 0 set). Guess: They
           probably can't time the VRAM load cycle closely enough while the
           graphics engine is running.
       7  (not 864/964) Enable EPROM Write. If set enables flash memory write
           control to the BIOS ROM address
Note: both index 38h and 39h must be enabled to access this register.

3d4h index 52h (R/W):  Extended BIOS Flag 1 Register                   (80x +)
bit  0-7  Scratch Pad
     0-3  (Diamond) Table entry ?
       4  (Diamond) VCLK doubler
       5  (Diamond) Interlace/NI
     6-7  (Diamond) Vsync/Hsync

3d4h index 53h (R/W):  Extended Memory Control 1 Register              (80x +)
bit  0-1  (80x) Enable Write Per Bit MB1,MB0.
     0-3  (928) Enable Write Per Bit MB3,MB2,MB1,MB0
           Enables Write Per Bit Flags for each 1MB memory bank.
       0  (864/964) ENB WPB. Enable Write Per Bit. Enables Write Per Bit for