s3.txt

比较详尽的VGA端口寄存器的文档

The entire S3 family are basically 8514/As with a VGA front-end.
Hardwired Bit-Blt, fill and line drawfunctions.


  S3  86c911     184pin 1Mbyte, 1280x1024x16c, 1024x768x256c, 640x480x32kc
  S3  86c911A    184pin Same as 924??. Corrects a bug in 1280 modes.
  S3  86c924     184pin Support for 24-bit modes.
  S3  86c801     160pin as '928, but limited to 2MB DRAM & no 32bit
                   acceleration- '801 is the ISA version
  S3  86c805     184pin same as '801 but for Local Bus
  S3  86c805i      as 805, but can interleave two banks of DRAM
  S3  86c805p      PCI version of the '805
  S3  86c928     208pin 24bit color, 4MB D/VRAM Accelerated 4/8/16/32bit
  S3  86c928p      PCI version of the '928
  S3  Vision964  208pin. VRAM 64bit chip. Max 8MB (1600x1200 32bit)
  S3  Vision864  208pin. As 964, but with max 4MB DRAM.
  S3  86c732       "Trio32" Integrated '864, DAC and clock chip. 32bit memory
                    path
  S3  86c764     208pin. "Trio64" Integrated '864, DAC and clock chip
  S3  86c866
  S3  86c868     as '864, but with video support
  S3  86c968     as '964, but with video support


  The S3 chip only works in AT and better units as it uses full
  16 bit I/O addresses.

  The S3 has an 8514/A style bitblt engine which uses a number of I/O
  addresses with the lowest 10 bits = 2E8h (4AE8h, 82E8h, BEE8h...).

  Please note that this may conflict with Com4 ports at 2E8h-2EFh !!!


102h (R/W):  Setup Option Select Register (SETUP_MD)
bit    0  SLP MODE. When clear the chip ignores I/O and memory accesses. The
          video system will continue running as before the bit was cleared.
Note: This register can only be accessed when in setup mode, which is
 controlled either by 3C3h bit 0 or 46E8h bit 4. When in setup mode all other
 VGA and extended registers are disabled.

3B8h (R/W):  MDA-Mode Control Register (MDA_MODE)
bit    3  DSP ENB. Enable Display. 1: Blanked, 1: Video enabled
       5  TXT BLK. Text Blinking enabled if set

3B8h (R/W):  HGC-Mode Control Register (HGC_MODE)
bit    1  GRPH MODE. Enable Graphics Mode. 0: Text, 1: 720x348 Graphics
       3  DSP ENB. Enable Display. 0: Blank, 1: Video enabled
       5  TXT BLK. Text Blinking enabled if set
       7  HGC PAGE. Select Hercules Graphics Video Page 1. 0: Display from
          B000h (page 0), 1: Display from B800h (page 1)

3B9h (W):  HGC-Set Light Pen Flag Register (HGCV_SLPEN)
Any write to this register will set the Light Pen Latch

3BAh (R):  MDA Status Register (MDA_STS)
bit    0  HSY. Horizontal Sync Active. Border or Blanking active if set
       3  TEST. B/W Video enabled if set

3BAh (R):  HGC Status Register (HGC_STS)
bit    0  HSY. Horizontal Sync Active. Border or Blanking active if set
       1  LPF. Light Pen Flag on if set
       3  V-DT. Black/White Video enabled if set
       7  /VSY. Vertical Sync Inactive. Vertical Sync active if set

3BBh (W):  Reset Light Pen Flag Register
Any write to this register will clear the Light Pen Latch

3BFh (W):  HGC Configuration Register
bit    0  ENB GRPH. Enable Graphics. 0: Force Text mode, 1: Allow Graphics
          mode
       1  ENB PAGE. Enable Page. 0: 3B8h bit 7 can't be set (always use page
          0), 1: 3B8h bit can be set enabling both pages

3C4h index 08h (R/W):  "PLL Unlock"                                 (732/764)
bit  0-?  Write 6 to unlock the PLL registers (3C4h index 10h-13h,15h..),
          write 0 to lock.

3C4h index 09h (R/W):                                               (732/764)
3C4h index 0Ah (R/W):                                               (732/764)
3C4h index 0Bh (R/W):                                               (732/764)
3C4h index 0Dh (R/W):                                               (732/764)

3C4h index 10h W(R/W):  "Memory PLL Data"                           (732/764)
bit  0-4  N1. Frequency divider. Stored as 1-31, actual value 3-33
     5-7  N2. Divides the frequency. 0: /1, 1: /2, 2: /4, 3: /8
    8-14  M.  Quotient. Stored as 1-127, actual value 3-129
Note: Frequency is (M/N1)/(1 << N2) *base frequency.M and N1 are the actual
      values, not the stored ones. Typically the base frequency is 14.318 MHz.

3C4h index 12h W(R/W):  "Video PLL Data"                            (732/764)
bit  0-4  N1. Frequency divider. Stored as 1-31, actual value 3-33
     5-7  N2. Divides the frequency. 0: /1, 1: /2, 2: /4, 3: /8
    8-14  M.  Quotient. Stored as 1-127, actual value 3-129
Note: Frequency is (M/N1)/(1 << N2) *base frequency.M and N1 are the actual
      values, not the stored ones. Typically the base frequency is 14.318 MHz.

3C4h index 15h (R/W):                                               (732/764)
bit    4  Set in 1x 16bit -> 2x 8bit pixel mode
       5  After updating a clock register set write this bit 3 time.
          First 0, then 1 and finally 0.

3C4h index 18h (R/W):                                               (732/764)
bit    7  Set in 1x 16bit -> 2x 8bit pixel mode

3d4h index 2Dh (R):
bit  0-7  Extended Chip ID. Always 88h ?

3d4h index 2Eh (R):  "New chip ID"                               (7xx,866,x68)
bit  0-7  Extended Chip ID (if index 30h is E0h/E1h)
             10h  86c732 (Trio32)
             11h  86c764 (Trio64)
             80h  86c866
             90h  86c868
             B0h  86c968

3d4h index 2Fh (R):  Revision                                    (7xx,866,x68)
bit  0-7  Revision code
     4-7  (86c764) 8 for the 86c765 (Trio64 V+) ??

3d4h index 30h (R):  CR30 Chip ID/REV register
bit  0-7  Chip ID:
             81h  86c911
             82h  86c911A/924
             90h  86c928 original
             91h  86c928 C-step
             94h  86c928 D-step
             95h  86c928 E-step
             A0h  86c801/805 A or B-step
             A2h  86c801/805 C-step
             A5h  86c801/805 D-step
             A6h  86c801/805 P-step
             A8h  86c801/805 I-step
             B0h  86c928PCI
             C0h  Vision 86c864
             C1h  Vision 86c864P
             D0h  Vision 86c964
             D1h  Vision 86c964P
         E0h,E1h  Trio32/64, 86c866,86c868,86c968, See index 2Eh

3d4h index 31h (R/W):  CR31 Memory Configuration Register
bit    0  Enable Base Address Offset (CPUA BASE). Enables bank operation if
          set, disables if clear.
       1  Two Page Screen Image. If set enables 2048 pixel wide screen setup
       2  VGA 16bit Memory Bus Width. Set for 16bit, clear for 8bit
       3  Use Enhanced Mode Memory Mapping (ENH MAP). Set to enable access to
           video memory above 256k.
     4-5  Bit 16-17 of the Display Start Address. For the 801/5,928 see index
           51h, for the 864/964 see index 69h.
       6  High Speed Text Display Font Fetch Mode. If set enables Page Mode
          for Alpha Mode Font Access.
       7  (not 864/964) Extended BIOS ROM Space Mapped out. If clear the area
           C6800h-C7FFFh is mapped out, if set it is accessible.

3d4h index 32h (R/W):  CR32 Backwards Compatibility 1
bit  0-1  Character Clock Period (CK-CLK).
            0: As IBM (8 or 9 dots), 1: 7 dots, 2: 9 dots
       2  Force High Character Clock. Forces full character clock for
          horizontal timing (for CGA and HGC emulation), rather than 1/2 dot
          clock rate
       3  Backward Modes. Clear for VGA, set for MDA, CGA, EGA, HGC
       6  Fix VGA Screen Page with IBM VGA Memory Mapping using Display Start
          Address bit 16-17 (3d4h index 31h bit 4-5)
       7  (928,964) Serial Out Tri-State. If set the SC, SOE0 and SXNR pins
           are tri-stated

3d4h index 33h (R/W):  CR33 Backwards Compatibility 2
bit    1  Disable VDE Protection. Disables the function of 3d4h index 11h bit
          7 on 3d4h index 7 bit 1,6.
       3  VCLK = -DCLK. If set VCLK is inverted DCLK, if clear it is inverted
          DCLK or DCLK/2
       4  Lock Video DAC Writes. If set disables writes to the RamDAC.
       5  Blank/Border Select. If set the blank signal will be the same as
          the active display enable timing, if clear blank comes earlier than
          the display enable by including the border area.
       6  Lock Palette/Overscan Registers if set.
       7  Overrides the CGA "enable video" in 3D8h bit 3 if set.

3d4h index 34h (R/W):  CR34 Backward Compatibility 3
bit  0-3  BIOS use.
       0  Set if address is multiplied with 4 (16color modes ?)
       4  (9xx) Enable Data Transfer Position Control (ENB DTPC). If set the
          Data Transfer position (When a new row should be loaded into the
          shift register of the VRAM) is controlled by 3d4h index 3Bh, if
          clear by 3d4h index 0.
       5  Lock 8/9 Dots (LOCK 8/9D). Lock the character clock period (3C4h
          index 1 bit 5) if set. When emulating EGA the horizontal timing
          registers are programmed for 8 dot character clock.
       7  Lock Clock Select (LOCK CKSL). If set the bits 2-3 of the
          Miscellaneous Output register (3C2h) are locked.

3d4h index 35h (R/W):  CR35 CRT Register Lock
bit  0-3  CPU Base Address. 64k bank number. For the 801/5 and 928 see 3d4h
          index 51h bits 2-3. For the 864/964 see index 6Ah.
       4  Lock Vertical Timing Registers (LOCK VTMG). Locks 3d4h index 6, 7
          (bits 0,2,3,5,7), 9 bit 5, 10h, 11h bits 0-3, 15h, 16h if set
       5  Lock Horizontal Timing Registers (LOCK HTMG). Locks 3d4h index
          0,1,2,3,4,5,17h bit 2 if set
       6  (911/924) Lock VSync Polarity.
       7  (911/924) Lock HSync Polarity.

3d4h index 36h (R/W):  CR36 Reset State Read 1
bit  0-1  (R) System Bus Select. 0: EISA (805 only), 1: Originally "386/486
           local bus" later "VESA local bus", 2: MCA (911/24), PCI bus (805P
           /928P +) or 8bit (801/5,928 undoc), 3: ISA (not 805)
       2  (911-928) VGA ROM Width. Set if 8bit, clear if 16bit
     2-3  (864/964) Memory Page Mode Select. 2: Extended Data Out (EDO) Mode,
           3: Fast Page Mode
       3  (911/24) VRAM. Set if using VRAM (should always be set)
          (801/5,928) VGA BIOS ROM Enable. If set BIOS is C0000h-C7FFFh, if
           clear C0000h-C5FFFh plus C6800h-C7FFFh
       4  (911/24) Set if display memory is dedicated (Should always be set)
          (801/5,928 ISA Bus) Address Bit Range for MEMCS16. LA[17-23] if set,
            also SA16 if clear
          (805,928 Local Bus) SAUP2/ROMCS Select. If clear SAUP2 pin is ROMCS,
            if set it is unchanged.
          (864,964) Enable Video BIOS Access (VL-Bus) if set.
       5  (911/24) Video memory. 0: 1Mb, 1: 512Kb
     5-7  (not 911/924) Display Memory Size. 0: 4MB, 2: 3MB, 3: 8MB, 4: 2MB,
            5: 6MB, 6: 1MB, 7: 512Kb
       7  (911/24) Display Memory WPB is available if set (should always be
            set)
Note: These bits are latched from pins PD[0-7] on reset

3d4h index 37h (R/W):  CR37 Reset State Read 2
bit    0  (ISA Bus) Setup SEL for ISA bus. If set SEL is 46E8h bit 4, bit 5 if
           clear
          (Local Bus) VGA Enable. Enables VGA chip if set
       1  (911/24) VRAM Display Memory Speed. Set for Fast Page Mode (80ns
           VRAM), clear for Page Mode (100ns VRAM).
          (801/5,928) Reserved(1)
          (964) Test Mode enabled if clear. All outputs are tri-stated
       2  (911/24) 386/486 System Setup is ISA style if set, MCA style if
           clear
          (801/5,928) Extended Monitor Identification. Extends bit 5-7
          (964 CVL-Bus) Video BIOS ROM Size. Set for 32K, clear for 64K
       3  (Local Bus) LOCA Signal Select. Tri-state signal if set, Level
           signal if clear