compaq.txt

比较详尽的VGA端口寄存器的文档

    Compaq Super VGA chips.

There are 3 "Families" of Compaq VGA chips:

Integrated Video Graphics System (IVGS aka Starlight):
Supports 640x480x16c. BitBLT functions

Advanced VGA System (AVGA aka Stardust):
Supports 800x600x16c and 640x480x256c. BitBLT functions.

QVision:
Supports 1024x768x256c. Newer versions support 1280x1024 and/or TrueColor.
Hardware Cursor, BitBLT.

  QVision        (128084)   Max 1MB (Victory)
  QVision 1024              Max 2MB (V32 ?)
  QVision 1280   (139148)   Max 2MB (V32)

The QVision 2000 is actually a Matrox MGA-II (Ultima) clone.


3C2h (W):  Miscellaneous
bit 2-4  (QVision) Clock select. In AVGA mode the two lower bits selects
          one of 4 clocks, in QVision mode (3CEh index 0Fh <> A5h) these
          3 bits selects 1 of 8 other clocks, thus there are 12 clocks
          available on the QVision.
Note: This is a standard VGA register, all other bits follow VGA standard.
      This register can be read at 3CCh.

3CEh index 0Bh (R/W):
bit    0  ??
       1  If set the ROM is 16bit wide, 8 if clear
       2  If set video memory is 16bit wide, 8 if clear
       3  Blanks screen if set ??
       4  ??

3CEh index 0Ch (R):  Controller Version
bit  3-7  Version.
            03h: IVGS
            05h: AVGA
            06h: Original QVision
            0Eh: QVision 1024 or 1280
            10h: Advanced VGA Port (What is this?)

3CEh index 0Dh (R/W):  Extended Controller Version

3CEh index 0Eh (R/W):  Extended Controller Capabilities

3CEh index 0Fh (R/W):  Environment Register
bit  0-3  writing 5 to this register unlocks the extended registers.
     4-7  (QVision) 0Ah if in AVGA mode, 0 if in QVision mode
Note: The QVision has a specific mode for AVGA support (Mode 29h and 2Eh),
      where the AVGA accelerator function and registers are used.

3CEh index 10h (R/W):  BLTConf
bit  0-1  ??
       2  (QVision) If set the 2xxxh-3xxxh register block is mapped at 4xxxh
            -5xxxh
     3-4  (chip ?) Video interrupt. 0= Active Low, 1,3=Active High, 2=Disabled.
       3  (QVision) If set enables access to some of the extended registers ?
       5  Tri-state if set
       6  ??
       7  (AVGA) If set the screen goes all white or black ?

3CEh index 11h (R/W):
bit    0  ??

3CEh index 40h (R/W):  Control Register 0
bit    0  If set accesses to the upper bank (0A8000h-0AFFFFh) are calculated
          from 0A8000h (I.e.. to create a 64K unified window index 46h should
          be programmed with a value 8 larger than index 45h). If clear
          accesses are relative to 0A0000h (I.e.. use same value in index 45h
          and 46h).
       1  If set the memory layout is different ?
     2-7  ??

3CEh index 41h (R/W):
bit  0-2  ??

3CEh index 42h (R/W):  CRTC Overflow
bit  0-1  Bit 8-9 of the Display Offset. Bits 0-7 are in 3d4h index 13h.
     2-4  Display start Address bits 16-18. Bits 0-15 are in 3d4h index
          0Ch,0Dh
       5  ??
       6  If set moves the display ~50 lines ??
       7  ??

3CEh index 43h (R/W):
bit  0-7  ??

3CEh index 44h (R/W):
bit  0-7  ??

3CEh index 45h (R/W):  Page Register 0
bit  0-7  Bank number in 4KB blocks for accesses to A000h-A7FFh.
          (AVGA) In 16c planar modes the bank is in units of 1Kb
          (QVision 1280) If 23C7h bit 4 is set the bank is in units of 16Kb

3CEh index 46h (R/W):  Page Register 1
bit  0-7  Bank number in 4KB units for accesses to A800h-AFFFh
          If index 40h bit 0 is set this value must be 8 larger than the value
          in index 45h (8*4k = 32k) to provide a 64k unified window. If index
          40h bit 0 is clear this value should be the same as in index 45h.

3CEh index 48h (R/W):
bit  0-3  High Area Memory (0=disabled, 1-0Eh = the 1MB boundary the HMA
          starts at). The HMA is a 1MB continuos mapping of the video buffer.
     0-7  (QVision) Lower 8 bits of the HMA start address

3CEh index 49h (R/W):
bit  0-7  (QVision) Upper 8 bits of the HMA start address

3CEh index 50h (R/W):                                                (QVision)
bit  0-2  ??
     3-6  Monitor (0,2,6??)
             00h  Compaq Internal Monitor
             02h  Compaq 16" Advanced Graphics Color Monitor
             03h  Compaq 1024 Color Monitor
             04h  QVision 200 (20") Color Monitor
             05h  Compaq SVGA Color Monitor
             06h  QVision 150 (15") Color Monitor or
                  Compaq 151 FS Color Monitor
             0Eh  Compaq 14" VGA Monitor (31.5 kHz)
       7  ??

3CEh index 51h (R/W):                                                (QVision)
bit    0  Divides clock by ~3.5 if set ???
     1-2  ??
       3  If clear blanks the left half of the display ??
       4  Clock ??
       5  Horizontal Retrace End bit 5. Bits 0-4 are in 3d4h index 5 bits 0-4.
       6  Vertical Total bit 10. Bits 0-7 are in 3d4h index 6, bits 8&9 are
          in 3d4h index 7.
       7  Vertical Retrace Start bit 10. Bits 0-7 are in 3d4h index 10h.

3CEh index 52h (R/W):
bit    0

3CEh index 54h (R/W):  Available Memory                              (QVision)
bit  0-7  Video Memory. 2: 512k, 4: 1024k, 8: 2048k
Note: For the QVision 1024, 0 apparently means 1024KB.

3CEh index 55h (R/W):  PLL Clock
bit  0-7  ??

3CEh index 56h (R/W):  Controller Capabilities                       (QVision)
bit  0-1  ??
       2  Set for QVision 1280, clear for QVision 1024
     3-7  ??

3CEh index 57h (R/W):  Controller Capabilities II                    (QVision)
bit  0-7  ??

3CEh index 5Ah (R/W):                                                (QVision)
bit  0-5  1 for copy, 2 for fill
     6-7  Set to 3 or 0 ??

3CEh index 80h (R/W):                                                      (?)
bit  2-3  2=Plasma system.
     4-6  Palette option: 1=Standard palette, 2=Option B, 5=option A,
            6=option C.

3CEh index 81h (R/W):                                                      (?)
bit   2  Set for Palette option A-C and Standard palette, clear for option D.

13C6h - 13C9h are implemented as DAC regs REG0A,REG0B,REG08 and REG09 for the
 QVision (DAC has RS2 = 0 and RS3 = 1).

23C0h W(R/W): Source Address                                 (IVGS, AVGA only)
bit  0-15  Address of source in DWORDs (256colors) or bytes (16colors).
           (AVGA) Bit 16-17 are in 23C4h.
           The exact address and size of the BitBLT can be adjusted by
           33C0h,33C1h,33C8h and 33C9h

23C2h (R/W):  Width of area                                  (IVGS, AVGA only)
bit   0-7  Width in DWORDs of the Blit area.

23C2h W(R/W): Width of BitBLT operation                         (QVision only)
bit   0-9  Width of the BitBLT area in pixels

23C4h W(R/W): Height of the BitBLT area
bit   0-9  Number of lines in Blit area.
    10-11  (AVGA) Bit 8-9 of the Scanline Width. Bit 0-15 are in
    12-13  (AVGA) Bit 16-17 of the distance. Bit 0-15 are in 23CCh.
    14-15  (AVGA) Bit 16-17 of Source address. Bit 0-15 are in 23C0h.

23C6h (R/W):

23C7h (R/W):
bit     2  Set to enable Linear Frame Buffer.
        4  Set to use 16K banks, clear to use original 4K banks

23CAh W(R/W):  Scanline width.                               (IVGS, AVGA only)
bit  0-15  Width of destination in DWORDs (256color) or bytes (16color).
           Negative if moving backwards.

23CCh W(R/W): Destination Address                            (IVGS, AVGA only)
bit  0-15  Distance between the Destination and the Source Address in DWORDs
           (256colors) or bytes (16colors).
           (AVGA) Bit 16-17 are in 23C4h bit 12-13.

23CCh W(R/W):  Scanline Width                                        (QVision)
bit   0-  Bytes per scanline in the destination in units of 4 (DWORDs).

23CEh W(R/W):  Scanline width.                               (IVGS, AVGA only)
bit  0-15  Width of destination in DWORDs. Negative if moving backwards.
Note: one must be source and the other destination width

33C0h (R/W):                                                 (IVGS, AVGA only)
bit  0-7  Start pixel of BitBLT source

33C1h (R/W):                                                 (IVGS, AVGA only)
bit  0-7  Ending pixel of BitBLT destination

33C7h (R/W):                                                 (IVGS, AVGA only)


33C8h (R/W):                                                 (IVGS, AVGA only)
bit  0-1
Note: this is the same register as 3CEh index 3  ??

33C9h (R/W):                                                 (IVGS, AVGA only)

33CAh W(R/W):  Fore/Back ground color ?

33CCh W(R/W):  Fore/Background color
Note: Apparently the Fore/Background color registers must be written twice to
      work properly.

33CEh (R/W):  COP Status/Command
bit    0  (R) If set the CoProcessor is busy.
     0-5  (W) 11h = Copy. 9 = Fill.
       6  (W) Copy/Fill backwards if set

33CFh (R/W):

63C0h W(R/W): Source Bitmap X-address                           (QVision only)
bit   0-9  The X co-ordinate of the start of the Source Data.

63C2h W(R/W): Source Bitmap Y-address                           (QVision only)
bit   0-9  The Y co-ordinate of the start of the Source Data.

63C4h (R/W):

63C5h (R/W):

63CAh (R/W):
bit   0-2  1=4bit packed, 3=8bit packed, 5= 15bit, 7=24 bit (packed as RGBa)
        6  After loading the BitMap Address and Size registers, wait for this
           bit to be 0 before setting final registers and starting the
           command.
        7  Wait for this bit to be 0, before loading the Source/Destination
           address and BitMap size registers.

63CBh (R/W):
bit     0  Set for 2Mb?
      2-3  Scanline Width. 0: 512 pixels/line, 1: 1024 pixels/line, 2: 2048
           pixels/line
      4-6  Set to 7 ?

63CCh W(R/W): Destination Bitmap X-address                      (QVision only)
bit   0-9  The X co-ordinate of the start of the Destination Data

63CEh W(R/W): Destination Bitmap Y-address                      (QVision only)
bit   0-9  The Y co-ordinate of the start of the Destination Data

83C4h ():  Virtual Controller Select                            (QVision only)

83C6h-83C9h  Extra DAC registers (RS2 = 1) on the AVGA and QVision boards

93C6h-93C9h  Extra DAC registers (RS2 = 1, RS3 = 1) on QVision boards

93C6h W(R/W): Hardware Cursor Y-position
bit   0-9  The X-position of the right pixel of the hardware cursor.

93C8h W(R/W): Hardware Cursor X-position
bit   0-9  The Y-position of the lower scanline of the hardware cursor.