paradise.txt

比较详尽的VGA端口寄存器的文档

bit  0-1  Selects the number of VCLK cycles to delay Hsync.
          If bit 7 clear:  0: 0, 1: 1, 2: 2, 3: 3
          If bit 7   set:  0: 4, 1: 5, 2: 6, 3: 7
       2  If set enables Auto-Centering and Vertical Expansion
       3  If set Vertical Expansion is selected, if clear Auto-Centering
       4  Set if LCD display enabled
       5  Set if external display (CRT) enabled
       6  Frame Pulse (FP) Timing Select. If set selects ON time during second
          horizontal line, if clear during first horizontal line
       7  Plasma Panel Interface. If set selects 8bits/2pixel interface, if
          clear selects 4bits/pixel interface

3d4h index 33h (R/W):  PR1A Flat Panel Control 2                (WD90c2x only)
bit  0-1  Memory Refresh Cycles: 0,2: determined by CRT controller,
            1: 1 cycle/line, 3: 2 cycles/line
       2  If set Shading Method is Pulse Width Modulation, if clear Frame Rate
          Modulation.
       3  If set selects 4bit single LCD, if clear selects 8bit single LCD
     4,7  Panel Resolution. 0: 640x480, 1: 1280x1024, 2. 1024x768, 3. 800x600
     5-6  STN Panel Type. 0: Not a STN Panel, 1: 8bit STN, 3: 16bit STN

3d4h index 34h (R/W):  PR1B Flat Panel Unlock Register          (WD90C2x Only)
bit  0-2  Write 6 to unlock Shadow registers
     5-7  Write 5 to unlock Flat Panel Registers (3d4h index 31h-33h,37h,3Bh,
           3Ch,3Eh,3Fh)
Note: Write A6h to unlock all WD90c2x extensions

3d4h index 35h (R/W):  PR30 Mapping RAM Unlock                  (WD90c2x only)
bit  0-7  Write 30h to unlock the Mapping RAM Registers (3d4h index 38h-3Ah).

3d4h index 37h (R/W):  PR41 Vertical Expansion Initial Value    (WD90c2x only)
bit  0-7  Selects the line to repeat at the top of the frame when Vertical
          Expansion is selected.

3d4h index 38h (R/W):  PR33 Mapping RAM Address Counter         (WD90c2x only)
bit  0-7  The address in Mapping RAM that will be affected by the next access
          to index 39h. Any read or write to index 39h will increment this
          register.
Note: Should only be access with 8bit I/O operations

3d4h index 39h (R/W):  PR34 Mapping RAM Data Register           (WD90c2x only)
bit  0-7  The byte in Mapping RAM addressed by index 38h can be accessed here
Note: Should only be access with 8bit I/O operations

3d4h index 3Ah (R/W):  PR35 Mapping RAM and Power-Down Control  (WD90c2x only)
bit    1  If set enables the NTSC weighting equation: I=0.3R + 0.59G + 0.11B
       3  If set bypasses the Mapping RAM, if clear uses Mapping RAM for gray
          scale to gray shade mapping
       5  If set disables the VGA controller
       6  If set (and 3d4h index 3Fh bit 7 is set) enables internal clock
          divided by 8
       7  If set (and 3d4h index 3Fh bit 7 is set) enters System Power-down
          mode - MCLK and VCLK are turned off

3d4h index 3Bh (R/W):  PR36 Panel Height Select                 (WD90c2x only)
bit  0-7  The number of lines (-1) in a single panel.

3d4h index 3Ch (R/W):  PR37 Flat Panel Blinking Control         (WD90c2x only)
bit  0-2  Cursor Blink Rate. 1: 8 frames on/8 off, 2: 16 on/16 off,
            3: 32, 4: 64, 5: 128, 7: no cursor blinking
     3-5  Character Blink Rate. 1: 8 frames on/8 off, 2: 16 on/16 off,
            3: 32, 4: 64, 5: 128, 7: no cursor blinking
       6  Shift Clock Polarity. If set data changes with falling edge of XSCLK
          Data should be latched on rising edge. If clear data changes on the
          rising edge of XSCLK and should be latched on the falling edge.
       7  LCD Latch Pulse (LP) Signal Select. If clear LP is disabled during
          Vertical Blanking, if set LP is free running.

3d4h index 3Dh (R/W):  PR18A CRTC Vertical Timing Overflow         (WD90c30 +)
bit    0  Vertical Total bit 10 (3d4h index 6)
       1  Vertical Display Enable bit 10 (3d4h index 12h)
       2  Start Vertical Retrace bit 10 (3d4h index 10h).
       3  Start Vertical Blank bit 10 (3d4h index 15h).
       4  Line Compare bit 10 (3d4h index 18h).

3d4h index 3Eh (R/W):  PR39 Color LCD Control                   (WD90c2x only)
bit    0  LP Polarity Select. If set LP has reverse polarity
       1  FP Polarity Select. If set FP has reverse polarity
       2  Enable CRT VSYNC and HSYNC if set, if clear the VSYNC and HSYNC
          outputs are inactive high
       3  Enable Reverse Video. See 3d4h index 31h bit 4
       5  Set for Color Panels, clear for Mono Panels.
       6  Color LCD Panel Border Select. 0: White, 1: Black
       7  Enable LP Border Control. If set generates a special LP pulse to
          latch border information

3d4h index 3Eh (R/W):  PR18 CRT Vertical Timing                     (c33 only)
bit    0  Some sort of Vertical timing ?
       1  Moves the display up ~32 lines ?? if set. Guess: V Blanking End ?
       2  Some sort of timing (looses sync if set)
       5  Bit 8 of the Horizontal Total (3d4h index 0)
       6  CRTC Display Start Address bit 18. Bits 0-15 are in 3d4h index
          0Ch,0Dh and bits 16-17 are in 3CEh index 0Dh bits 3-4.
       7  Set if 2MB video memory

3d4h index 3Fh (R/W):  PR44 Power-Down and Memory Refresh
                       Control Register                         (WD90c2x only)
bit  0-6  Memory Refresh Period
       7  Set to enable General Power-down

3d4h index 3Fh (R/W):  PR19 Signature Analyser                    (c33 only ?)

3D8h (W):  Color CGA Operation Register
bit    0  If set selects 80x25 text mode, if clear 40x25 text mode
       1  Set in graphics modes, clear in text modes.
       3  Set in BW modes, clear in color modes
       4  If set enables 640x200 BW mode
       5  If set enables blinking
Note: this register active in CGA emulation mode only

3D9h (W):  CGA Color Select Register
bit  0-3  Each bit controls the behavior of one color:
           Bit 0 controls Blue, 1: Green, 2: Red, 3: Intensity
          If set the bit has the following effect in each mode:
            Alphanumeric mode:  Selects the color for the border
            320x200 Graphics:   Selects the color for border and background
            640x200 Graphics:   Selects the color for foreground
       4  If set enables alternate color set in graphics mode
       5  Selects 320x200 color set. 0: backgr, Green, Red, Brown
            1: Backgr, Cyan, Magenta, White
Note: this register active in CGA emulation mode only

3DAh (R):  CRT Status Register CGA Operation
bit    0  If set blanking or border is active
       1  If set Light Pen Latch is set
       2  If set Light Pen Switch is closed
       3  If set Vertical Retrace is active
Note: this register active in CGA emulation mode only

3DEh (W):  AT&T/M24 Register
bit    0  If set selects AT&T/M24 400 line mode, if clear selects 200 line
       2  If set selects alternate font in plane 3, if clear standard font in
          plane 2
       3  If set 16KB Display page starts at BC00h:0, if clear at B800h:0
       6  If set the underline attribute selects white underlined foreground,
          if clear it selects blue foreground in color text modes
Note: This register is only used in ATT mode (3CEh index 0Ch bit 7 set)

23C0h W(R/W):                                                  (WD90c24+ only)
bit  0-7  Selects the register bank at 23C2h.
            0: System Control, 1: BitBLT, 2: Cursor, 3: (WD90c33) BitBLT 2
    8-11  Register Index (for read operations)
      12  If clear the index field is incremented for each read operation of
          23C2h/3
      13  (R) Invalid register block. Set if the currently selected register
           block doesn't exist
Note: The WD90c33 (and possibly the 26) has a different layout of these
      registers than the WD90c24 and 31.

23C2h W(R/W):                                                  (WD90c24+ only)
bit 0-11  Data to write to the index selected by bits 12-15
   12-15  Selects the index the write will go to
Note: The index registers are marked as index a/b where a is the register bank
      selected by 23C0h and b is the index from bit 12-15.

23C2h index 0/0 W(R/W):  Interrupt Status Register             (WD90c24+ only)
bit    0  Set if any interrupt is active
       1  Set if Interrupt 1 is active (VGA)
       2  Set if Interrupt 2 is active (BITBLT)
     3-6  Set if the corresponding interrupt is active
       7  Set if any of interrupts 7-10 are active
       8  Set if interrupt 7 is active
       9  Set if interrupt 8 is active
      10  Set if interrupt 9 is active
      11  Set if interrupt 10 is active

23C2h index 1/0 W(W):  BITBLT Control                        (WD90c24,31 only)
bit  0-1  BITBLT Source. 0: screen memory, 2: 32bit system I/O address
     2-3  Source format. 0: color, 1: mono from color comparators,
           2: fixed color (Fill), 3: mono from host
     4-5  BitBlt Destination. 0: screen memory, 2: 32bit system I/O address
       6  If set Blit source is linear, if clear rectangular
       7  If set Blit destination is linear, if clear rectangular
     8-9  BitBlt address mode. 0: planar, 1: packed or text mode
      10  If set Blit is bottom->top, right->left,
          if clear top->bottom, left->right.
      11  Activation/status bit. Set this bit to start blit operation
          The bit will be cleared when the operation is finished, and can be
          read to check when the next operation can be started.

23C2h index 1/0 W(W):  Drawing Engine Control 1                 (WD90c33 only)
bit    0  Last Pixel Off. Last Pixel not drawn if set
       1  Destination Select. If set destination is Host I/O or memory, if
          clear it is screen memory.
       2  Pattern Enable. Set if the source is an 8x8 pattern
     3-4  Source Format. Defines the format of the source data:
            0: Source is a Color bitmap
            1: Monochrome from Color Comparators
            2: Source is fixed color from the Foreground Color Register (index
                1/2 and 1/3)
            3: Source is monochrome image from the host
       5  Source Select. If set source data is from the Host I/O or memory, if
          clear it is from the screen memory.
       6  Major Row. If set delta Y is larger than delta X (linedraw).
       7  Y Direction. If set the blit Y direction is negative (bottom-to-top)
       8  X Direction. If set the blit X direction is negative (right-to-left)
    9-11  Drawing Mode.  0: Nop, 1: BitBLT, 2: Linestrip, 3: Trapetzoid Fill
            Strip, 4: Bresenham Linedraw

23C2h index 1/1 W(W):  BITBLT Control                       (WD90c24,c31 only)
bit    0  Destination transparency if set
       1  Reserved, must be 0
       2  If set matching pixels are opaque, transparent if clear.
       3  Monochrome transparency if set
     4-5  BitBLT Pattern Select. 0: no pattern, 1:source is an 8x8 pattern
       6  Update destination registers on completion of blit if set
       7  Quick start BitBLT when destination register (or source register if
          bit 6 is set) is written if set
       8  Y direction for line draw. 0: top -> bottom, 1: bottom -> top
       9  X or Y Major for line draw. 0: X major, 1: Y major
      10  Interrupt when blit completes if set
      11  If set enables line drawing, if clear enables BitBLT operation

23C2h index 1/1 W(W):  Drawing Engine Control 2                 (WD90c33 only)
bit  0-2  Color Expansion Data Bits/Host Write. 2: 2bits/CPU write (16bpp),
            3: 4bits/CPU write (8,16bpp)), 4: 8bits/CPU write (4,8,16bpp),
            5: 8 or 16 bits/CPU write (4,8,16bpp)
       3  Host BitBLT through Memory Port. 0: via I/O, 1: via Memory
       6  Command Buffer Empty
       7  Monochrome Transparency Source. 0: Off, 1: On
       8  Destination Transparency Polarity. 0: Negative, 1: Positive
       9  Destination Transparency Enabled if set
   10-11  Pixel Depth.  0: 4bits per pixel, 1: 8bpp, 2: 16bpp

23C2h index 1/2 W(R/W):  BITBLT Source Low
bit 0-11  Lower 12 bits of the pixel source address
          Addresses are in Dwords, 4 bytes for planar modes = 4 pixels, 1 byte
          (x4 planes) for planar modes = 8 pixels.

23C2h index 1/2 W(R/W):  BITBLT Source Low                  (WD90c24,c31 only)
bit 0-11  Lower 12 bits of the pixel source address

23C2h index 1/2 W(R/W):  X Source                               (WD90c33 only)
bit 0-11  Starting X coordinate of the source area

23C2h index 1/3 W(R/W):  BITBLT Source High                 (WD90c24,c31 only)
bit  0-8  Upper 9 bits of the pixel source address

23C2h index 1/3 W(R/W):  Y Source                               (WD90c33 only)
bit 0-11  Starting Y coordinate of the source area

23C2h index 1/4 W(R/W):  BITBLT Destination Low             (WD90c24,c31 only)
bit 0-11  Lower 12 bits of the pixel destination address
          Addresses are in Dwords, 4 bytes for planar modes, 1 byte (x4
          planes) for planar modes.

23C2h index 1/4 W(R/W):  X Destination                          (WD90c33 only)
bit 0-11  Starting X coordinate of the destination area

23C2h index 1/5 W(R/W):  BITBLT Destination High            (WD90c24,c31 only)
bit  0-8  Upper 9 bits of the pixel destination address

23C2h index 1/5 W(R/W):  Y Destination                          (WD90c33 only)
bit 0-11  Starting X coordinate of the destination area